Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems

Bosung Jeon; Taejin Jang; Seongjae Cho; Hyungcheol Shin; Woo Young Choi

doi:10.23919/SNW57900.2023.10183948

Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems

Bosung Jeon, Taejin Jang, Seongjae Cho, Hyungcheol Shin, Woo Young Choi

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Essential characteristics of synapse arrays in neuromorphic systems include scalability, low-power operation, and precise vector-matrix multiplication (VMM). This paper investigates an asymmetric dual-gate synapse array that offers a power-efficient weight transfer method. By reconfiguring the arrangement of asymmetric gates, a 16 F2 cell-sized synapse array was produced. In addition, the array was fabricated with a buried-bottom gate structure, minimizing cell size and line resistance.

Original language	English
Title of host publication	2023 Silicon Nanoelectronics Workshop, SNW 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	15-16
Number of pages	2
ISBN (Electronic)	9784863488083
DOIs	https://doi.org/10.23919/SNW57900.2023.10183948
State	Published - 2023
Event	26th Silicon Nanoelectronics Workshop, SNW 2023 - Kyoto, Japan Duration: 11 Jun 2023 → 12 Jun 2023

Publication series

Name	2023 Silicon Nanoelectronics Workshop, SNW 2023

Conference

Conference	26th Silicon Nanoelectronics Workshop, SNW 2023
Country/Territory	Japan
City	Kyoto
Period	11/06/23 → 12/06/23

Bibliographical note

Publisher Copyright:
© 2023 JSAP.

Access to Document

10.23919/SNW57900.2023.10183948

Cite this

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title = "Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems",

abstract = "Essential characteristics of synapse arrays in neuromorphic systems include scalability, low-power operation, and precise vector-matrix multiplication (VMM). This paper investigates an asymmetric dual-gate synapse array that offers a power-efficient weight transfer method. By reconfiguring the arrangement of asymmetric gates, a 16 F2 cell-sized synapse array was produced. In addition, the array was fabricated with a buried-bottom gate structure, minimizing cell size and line resistance.",

author = "Bosung Jeon and Taejin Jang and Seongjae Cho and Hyungcheol Shin and Choi, \{Woo Young\}",

note = "Publisher Copyright: {\textcopyright} 2023 JSAP.; 26th Silicon Nanoelectronics Workshop, SNW 2023 ; Conference date: 11-06-2023 Through 12-06-2023",

year = "2023",

doi = "10.23919/SNW57900.2023.10183948",

language = "English",

series = "2023 Silicon Nanoelectronics Workshop, SNW 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "15--16",

booktitle = "2023 Silicon Nanoelectronics Workshop, SNW 2023",

}

Jeon, B, Jang, T, Cho, S, Shin, H & Choi, WY 2023, Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems. in 2023 Silicon Nanoelectronics Workshop, SNW 2023. 2023 Silicon Nanoelectronics Workshop, SNW 2023, Institute of Electrical and Electronics Engineers Inc., pp. 15-16, 26th Silicon Nanoelectronics Workshop, SNW 2023, Kyoto, Japan, 11/06/23. https://doi.org/10.23919/SNW57900.2023.10183948

Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems. / Jeon, Bosung; Jang, Taejin; Cho, Seongjae et al.
2023 Silicon Nanoelectronics Workshop, SNW 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 15-16 (2023 Silicon Nanoelectronics Workshop, SNW 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems

AU - Jeon, Bosung

AU - Jang, Taejin

AU - Cho, Seongjae

AU - Shin, Hyungcheol

AU - Choi, Woo Young

PY - 2023

Y1 - 2023

N2 - Essential characteristics of synapse arrays in neuromorphic systems include scalability, low-power operation, and precise vector-matrix multiplication (VMM). This paper investigates an asymmetric dual-gate synapse array that offers a power-efficient weight transfer method. By reconfiguring the arrangement of asymmetric gates, a 16 F2 cell-sized synapse array was produced. In addition, the array was fabricated with a buried-bottom gate structure, minimizing cell size and line resistance.

AB - Essential characteristics of synapse arrays in neuromorphic systems include scalability, low-power operation, and precise vector-matrix multiplication (VMM). This paper investigates an asymmetric dual-gate synapse array that offers a power-efficient weight transfer method. By reconfiguring the arrangement of asymmetric gates, a 16 F2 cell-sized synapse array was produced. In addition, the array was fabricated with a buried-bottom gate structure, minimizing cell size and line resistance.

UR - https://www.scopus.com/pages/publications/85167413950

U2 - 10.23919/SNW57900.2023.10183948

DO - 10.23919/SNW57900.2023.10183948

M3 - Conference contribution

AN - SCOPUS:85167413950

T3 - 2023 Silicon Nanoelectronics Workshop, SNW 2023

SP - 15

EP - 16

BT - 2023 Silicon Nanoelectronics Workshop, SNW 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th Silicon Nanoelectronics Workshop, SNW 2023

Y2 - 11 June 2023 through 12 June 2023

ER -

Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems

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