Vectored-bloom filter implemented on FPGA for IP address lookup

Hayoung Byun; Qingling Li; Hyesook Lim

doi:10.23919/ELINFOCOM.2019.8706399

Vectored-bloom filter implemented on FPGA for IP address lookup

Hayoung Byun, Qingling Li, Hyesook Lim

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper presents an IP address lookup architecture constructed with a vectored-Bloom filter (VBF) to perform the longest prefix matching. The VBF is an efficient structure to obtain the output port of each input IP address without accessing an off-chip memory. This paper demonstrates that the proposed IP address lookup architecture parallelly implemented on an FPGA can achieve the high performance in terms of the search speed and the throughput.

Original language	English
Title of host publication	ICEIC 2019 - International Conference on Electronics, Information, and Communication
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9788995004449
DOIs	https://doi.org/10.23919/ELINFOCOM.2019.8706399
State	Published - 3 May 2019
Event	18th International Conference on Electronics, Information, and Communication, ICEIC 2019 - Auckland, New Zealand Duration: 22 Jan 2019 → 25 Jan 2019

Publication series

Name	ICEIC 2019 - International Conference on Electronics, Information, and Communication

Conference

Conference	18th International Conference on Electronics, Information, and Communication, ICEIC 2019
Country/Territory	New Zealand
City	Auckland
Period	22/01/19 → 25/01/19

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF), NRF-2017R1A2B4011254.

Publisher Copyright:
© 2019 Institute of Electronics and Information Engineers (IEIE).

Keywords

FPGA
Hardware accelerator
IP address lookup
Vectored-Bloom filter

Access to Document

10.23919/ELINFOCOM.2019.8706399

Cite this

Byun, H., Li, Q., & Lim, H. (2019). Vectored-bloom filter implemented on FPGA for IP address lookup. In ICEIC 2019 - International Conference on Electronics, Information, and Communication Article 8706399 (ICEIC 2019 - International Conference on Electronics, Information, and Communication). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/ELINFOCOM.2019.8706399

@inproceedings{e93a949a4f6b463597a0ac1087e2707c,

title = "Vectored-bloom filter implemented on FPGA for IP address lookup",

abstract = "This paper presents an IP address lookup architecture constructed with a vectored-Bloom filter (VBF) to perform the longest prefix matching. The VBF is an efficient structure to obtain the output port of each input IP address without accessing an off-chip memory. This paper demonstrates that the proposed IP address lookup architecture parallelly implemented on an FPGA can achieve the high performance in terms of the search speed and the throughput.",

keywords = "FPGA, Hardware accelerator, IP address lookup, Vectored-Bloom filter",

author = "Hayoung Byun and Qingling Li and Hyesook Lim",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF), NRF-2017R1A2B4011254. Publisher Copyright: {\textcopyright} 2019 Institute of Electronics and Information Engineers (IEIE).; 18th International Conference on Electronics, Information, and Communication, ICEIC 2019 ; Conference date: 22-01-2019 Through 25-01-2019",

year = "2019",

month = may,

day = "3",

doi = "10.23919/ELINFOCOM.2019.8706399",

language = "English",

series = "ICEIC 2019 - International Conference on Electronics, Information, and Communication",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ICEIC 2019 - International Conference on Electronics, Information, and Communication",

}

Byun, H, Li, Q & Lim, H 2019, Vectored-bloom filter implemented on FPGA for IP address lookup. in ICEIC 2019 - International Conference on Electronics, Information, and Communication., 8706399, ICEIC 2019 - International Conference on Electronics, Information, and Communication, Institute of Electrical and Electronics Engineers Inc., 18th International Conference on Electronics, Information, and Communication, ICEIC 2019, Auckland, New Zealand, 22/01/19. https://doi.org/10.23919/ELINFOCOM.2019.8706399

Vectored-bloom filter implemented on FPGA for IP address lookup. / Byun, Hayoung; Li, Qingling; Lim, Hyesook.
ICEIC 2019 - International Conference on Electronics, Information, and Communication. Institute of Electrical and Electronics Engineers Inc., 2019. 8706399 (ICEIC 2019 - International Conference on Electronics, Information, and Communication).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Vectored-bloom filter implemented on FPGA for IP address lookup

AU - Byun, Hayoung

AU - Li, Qingling

AU - Lim, Hyesook

N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF), NRF-2017R1A2B4011254. Publisher Copyright: © 2019 Institute of Electronics and Information Engineers (IEIE).

PY - 2019/5/3

Y1 - 2019/5/3

N2 - This paper presents an IP address lookup architecture constructed with a vectored-Bloom filter (VBF) to perform the longest prefix matching. The VBF is an efficient structure to obtain the output port of each input IP address without accessing an off-chip memory. This paper demonstrates that the proposed IP address lookup architecture parallelly implemented on an FPGA can achieve the high performance in terms of the search speed and the throughput.

AB - This paper presents an IP address lookup architecture constructed with a vectored-Bloom filter (VBF) to perform the longest prefix matching. The VBF is an efficient structure to obtain the output port of each input IP address without accessing an off-chip memory. This paper demonstrates that the proposed IP address lookup architecture parallelly implemented on an FPGA can achieve the high performance in terms of the search speed and the throughput.

KW - FPGA

KW - Hardware accelerator

KW - IP address lookup

KW - Vectored-Bloom filter

UR - http://www.scopus.com/inward/record.url?scp=85065867164&partnerID=8YFLogxK

U2 - 10.23919/ELINFOCOM.2019.8706399

DO - 10.23919/ELINFOCOM.2019.8706399

M3 - Conference contribution

AN - SCOPUS:85065867164

T3 - ICEIC 2019 - International Conference on Electronics, Information, and Communication

BT - ICEIC 2019 - International Conference on Electronics, Information, and Communication

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International Conference on Electronics, Information, and Communication, ICEIC 2019

Y2 - 22 January 2019 through 25 January 2019

ER -

Vectored-bloom filter implemented on FPGA for IP address lookup

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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Cite this