Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes

Eunseon Yu; Won Jun Lee; Jongwan Jung; Seongjae Cho

doi:10.1109/TED.2018.2808764

Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes

Eunseon Yu, Won Jun Lee, Jongwan Jung, Seongjae Cho

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

18 Scopus citations

Abstract

In this paper, we propose an ultrathin SiGe shell channel p-type FinFET for sub-10-nm technology nodes. Owing to the large valence band offset (VBO or ΔEv) between SiGe shell and Si fin, a hole quantum well is configured in the high-mobility SiGe region as the major conduction path. The proposed device is optimally designed and characterized in dc and ac. Here, high-κ/metal gate is adopted for strong gate controllability and the high degree of freedom in threshold voltage (V_th) adjustment. For a high reliability, modeling of the mobility (μ) and saturation velocity (v_sat) is carried out for different Ge fractions (x). The E_g and VBO are also determined for different x from empirical data. With the set of modeled values and various quantum-mechanical models, the proposed device has been simulated through rigorous 3-D technology computer-aided design simulation. The designed device shows a high scalability reaching down to L_g = 5 nm. At L_g of 5 nm with a driving voltage (V_DD) of-0.5 V, a current gain cutoff frequency (f_T) = 368.88 GHz, dynamic power = 0.055 fJ/μm, and an intrinsic delay (τ) = 0.37ps are achieved. This is confirmed by the potential low-power and high-speed operations with a strong gate controllability.

Original language	English
Pages (from-to)	1290-1297
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	65
Issue number	4
DOIs	https://doi.org/10.1109/TED.2018.2808764
State	Published - Apr 2018

Bibliographical note

Funding Information:
Manuscript received February 7, 2018; accepted February 20, 2018. Date of publication March 5, 2018; date of current version March 22, 2018. This work was supported by the Ministry of Trade, Industry and Energy under Grant 10052928 and Grant 10080513 and the Korea Semiconductor Research Consortium Support Program for the development of the future semiconductor devices. The review of this paper was arranged by Editor W. Tsai. (Corresponding author: Seongjae Cho.) E. Yu is with the Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, South Korea.

Publisher Copyright:
© 2012 IEEE.

Keywords

High mobility
high-κ/metal gate (HKMG)
low-power (LP) high-speed operation
p-type FinFET
quantum well (QW)
shell channel
SiGe
SiGe modeling
strong gate controllability
technology computer-aided design (TCAD) simulation
valence band offset (VBO)

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10.1109/TED.2018.2808764

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title = "Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes",

abstract = "In this paper, we propose an ultrathin SiGe shell channel p-type FinFET for sub-10-nm technology nodes. Owing to the large valence band offset (VBO or ΔEv) between SiGe shell and Si fin, a hole quantum well is configured in the high-mobility SiGe region as the major conduction path. The proposed device is optimally designed and characterized in dc and ac. Here, high-κ/metal gate is adopted for strong gate controllability and the high degree of freedom in threshold voltage (Vth) adjustment. For a high reliability, modeling of the mobility (μ) and saturation velocity (vsat) is carried out for different Ge fractions (x). The Eg and VBO are also determined for different x from empirical data. With the set of modeled values and various quantum-mechanical models, the proposed device has been simulated through rigorous 3-D technology computer-aided design simulation. The designed device shows a high scalability reaching down to Lg = 5 nm. At Lg of 5 nm with a driving voltage (VDD) of-0.5 V, a current gain cutoff frequency (fT) = 368.88 GHz, dynamic power = 0.055 fJ/μm, and an intrinsic delay (τ) = 0.37ps are achieved. This is confirmed by the potential low-power and high-speed operations with a strong gate controllability.",

keywords = "High mobility, high-κ/metal gate (HKMG), low-power (LP) high-speed operation, p-type FinFET, quantum well (QW), shell channel, SiGe, SiGe modeling, strong gate controllability, technology computer-aided design (TCAD) simulation, valence band offset (VBO)",

author = "Eunseon Yu and Lee, {Won Jun} and Jongwan Jung and Seongjae Cho",

note = "Funding Information: Manuscript received February 7, 2018; accepted February 20, 2018. Date of publication March 5, 2018; date of current version March 22, 2018. This work was supported by the Ministry of Trade, Industry and Energy under Grant 10052928 and Grant 10080513 and the Korea Semiconductor Research Consortium Support Program for the development of the future semiconductor devices. The review of this paper was arranged by Editor W. Tsai. (Corresponding author: Seongjae Cho.) E. Yu is with the Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, South Korea. Publisher Copyright: {\textcopyright} 2012 IEEE.",

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N1 - Funding Information: Manuscript received February 7, 2018; accepted February 20, 2018. Date of publication March 5, 2018; date of current version March 22, 2018. This work was supported by the Ministry of Trade, Industry and Energy under Grant 10052928 and Grant 10080513 and the Korea Semiconductor Research Consortium Support Program for the development of the future semiconductor devices. The review of this paper was arranged by Editor W. Tsai. (Corresponding author: Seongjae Cho.) E. Yu is with the Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, South Korea. Publisher Copyright: © 2012 IEEE.

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N2 - In this paper, we propose an ultrathin SiGe shell channel p-type FinFET for sub-10-nm technology nodes. Owing to the large valence band offset (VBO or ΔEv) between SiGe shell and Si fin, a hole quantum well is configured in the high-mobility SiGe region as the major conduction path. The proposed device is optimally designed and characterized in dc and ac. Here, high-κ/metal gate is adopted for strong gate controllability and the high degree of freedom in threshold voltage (Vth) adjustment. For a high reliability, modeling of the mobility (μ) and saturation velocity (vsat) is carried out for different Ge fractions (x). The Eg and VBO are also determined for different x from empirical data. With the set of modeled values and various quantum-mechanical models, the proposed device has been simulated through rigorous 3-D technology computer-aided design simulation. The designed device shows a high scalability reaching down to Lg = 5 nm. At Lg of 5 nm with a driving voltage (VDD) of-0.5 V, a current gain cutoff frequency (fT) = 368.88 GHz, dynamic power = 0.055 fJ/μm, and an intrinsic delay (τ) = 0.37ps are achieved. This is confirmed by the potential low-power and high-speed operations with a strong gate controllability.

AB - In this paper, we propose an ultrathin SiGe shell channel p-type FinFET for sub-10-nm technology nodes. Owing to the large valence band offset (VBO or ΔEv) between SiGe shell and Si fin, a hole quantum well is configured in the high-mobility SiGe region as the major conduction path. The proposed device is optimally designed and characterized in dc and ac. Here, high-κ/metal gate is adopted for strong gate controllability and the high degree of freedom in threshold voltage (Vth) adjustment. For a high reliability, modeling of the mobility (μ) and saturation velocity (vsat) is carried out for different Ge fractions (x). The Eg and VBO are also determined for different x from empirical data. With the set of modeled values and various quantum-mechanical models, the proposed device has been simulated through rigorous 3-D technology computer-aided design simulation. The designed device shows a high scalability reaching down to Lg = 5 nm. At Lg of 5 nm with a driving voltage (VDD) of-0.5 V, a current gain cutoff frequency (fT) = 368.88 GHz, dynamic power = 0.055 fJ/μm, and an intrinsic delay (τ) = 0.37ps are achieved. This is confirmed by the potential low-power and high-speed operations with a strong gate controllability.

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KW - shell channel

KW - SiGe

KW - SiGe modeling

KW - strong gate controllability

KW - technology computer-aided design (TCAD) simulation

KW - valence band offset (VBO)

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EP - 1297

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 4

ER -

Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes

Abstract

Bibliographical note

Keywords

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