Tuning resistive switching parameters in Si3N4-based RRAM for three-dimensional vertical resistive memory applications

Sungjun Kim; Hyungjin Kim; Sunghun Jung; Min Hwi Kim; Sang Ho Lee; Seongjae Cho; Byung Gook Park

doi:10.1016/j.jallcom.2015.10.142

Tuning resistive switching parameters in Si₃N₄-based RRAM for three-dimensional vertical resistive memory applications

Sungjun Kim, Hyungjin Kim, Sunghun Jung, Min Hwi Kim, Sang Ho Lee, Seongjae Cho, Byung Gook Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

31 Scopus citations

Abstract

In this work, new 3D vertical RRAM device with silicon CMOS compatibility and the possible fabrication process are presented. RRAM devices based on Ni/Si₃N₄/p⁺-Si stack which are applicable in our proposed 3D vertical RRAM structure were fabricated in order to reveal the effects of switching layer thickness and compliant current on resistive switching parameters. Forming-less behavior can be easily achieved by controlling thickness of the Si₃N₄ layer. It is found that the high- and low-resistance state can be effectively modulated by the film thickness and compliance current, respectively.

Original language	English
Pages (from-to)	419-423
Number of pages	5
Journal	Journal of Alloys and Compounds
Volume	663
DOIs	https://doi.org/10.1016/j.jallcom.2015.10.142
State	Published - 5 Apr 2016

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2015R1A2A1A01007307).

Publisher Copyright:
© 2015 Elsevier B.V. All rights reserved.

Keywords

3D vertical structure
Compliance current
Film thickness
Resistive random-access memory (RRAM)
Silicon nitride (SiN)

Access to Document

10.1016/j.jallcom.2015.10.142

Cite this

@article{43f34017587a4ad7b8fce6a0659da282,

title = "Tuning resistive switching parameters in Si3N4-based RRAM for three-dimensional vertical resistive memory applications",

abstract = "In this work, new 3D vertical RRAM device with silicon CMOS compatibility and the possible fabrication process are presented. RRAM devices based on Ni/Si3N4/p+-Si stack which are applicable in our proposed 3D vertical RRAM structure were fabricated in order to reveal the effects of switching layer thickness and compliant current on resistive switching parameters. Forming-less behavior can be easily achieved by controlling thickness of the Si3N4 layer. It is found that the high- and low-resistance state can be effectively modulated by the film thickness and compliance current, respectively.",

keywords = "3D vertical structure, Compliance current, Film thickness, Resistive random-access memory (RRAM), Silicon nitride (SiN)",

author = "Sungjun Kim and Hyungjin Kim and Sunghun Jung and Kim, {Min Hwi} and Lee, {Sang Ho} and Seongjae Cho and Park, {Byung Gook}",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2015R1A2A1A01007307). Publisher Copyright: {\textcopyright} 2015 Elsevier B.V. All rights reserved.",

year = "2016",

month = apr,

day = "5",

doi = "10.1016/j.jallcom.2015.10.142",

language = "English",

volume = "663",

pages = "419--423",

journal = "Journal of Alloys and Compounds",

issn = "0925-8388",

publisher = "Elsevier BV",

}

TY - JOUR

T1 - Tuning resistive switching parameters in Si3N4-based RRAM for three-dimensional vertical resistive memory applications

AU - Kim, Sungjun

AU - Kim, Hyungjin

AU - Jung, Sunghun

AU - Kim, Min Hwi

AU - Lee, Sang Ho

AU - Cho, Seongjae

AU - Park, Byung Gook

N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2015R1A2A1A01007307). Publisher Copyright: © 2015 Elsevier B.V. All rights reserved.

PY - 2016/4/5

Y1 - 2016/4/5

N2 - In this work, new 3D vertical RRAM device with silicon CMOS compatibility and the possible fabrication process are presented. RRAM devices based on Ni/Si3N4/p+-Si stack which are applicable in our proposed 3D vertical RRAM structure were fabricated in order to reveal the effects of switching layer thickness and compliant current on resistive switching parameters. Forming-less behavior can be easily achieved by controlling thickness of the Si3N4 layer. It is found that the high- and low-resistance state can be effectively modulated by the film thickness and compliance current, respectively.

AB - In this work, new 3D vertical RRAM device with silicon CMOS compatibility and the possible fabrication process are presented. RRAM devices based on Ni/Si3N4/p+-Si stack which are applicable in our proposed 3D vertical RRAM structure were fabricated in order to reveal the effects of switching layer thickness and compliant current on resistive switching parameters. Forming-less behavior can be easily achieved by controlling thickness of the Si3N4 layer. It is found that the high- and low-resistance state can be effectively modulated by the film thickness and compliance current, respectively.

KW - 3D vertical structure

KW - Compliance current

KW - Film thickness

KW - Resistive random-access memory (RRAM)

KW - Silicon nitride (SiN)

UR - http://www.scopus.com/inward/record.url?scp=84952920699&partnerID=8YFLogxK

U2 - 10.1016/j.jallcom.2015.10.142

DO - 10.1016/j.jallcom.2015.10.142

M3 - Article

AN - SCOPUS:84952920699

SN - 0925-8388

VL - 663

SP - 419

EP - 423

JO - Journal of Alloys and Compounds

JF - Journal of Alloys and Compounds

ER -