TY - GEN
T1 - Timing error masking by exploiting operand value locality in SIMD architecture
AU - Sim, Jaehyeong
AU - Park, Jun Seok
AU - Paek, Seungwook
AU - Kim, Lee Sup
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/12/3
Y1 - 2014/12/3
N2 - A significant amount of energy is consumed by a voltage guardband to ensure error-free operations under the worsening PVT variations in modern processors. Circuit-level timing speculation has become a popular approach that increases energy efficiency by removing such guardband and tolerating occasional timing errors. However, SIMD processors suffer from a large throughput and energy efficiency loss induced by a conventional error correction mechanism which requires several extra cycles for each timing error. In this paper, we present an error masking scheme to eliminate the chances of performing the error correction. The error masking is done by allowing potential erroneous addition instructions to reuse the partial result of previous operations. We show that reuse can be applied to a large number of addition instructions by exploiting the observations that SIMD applications exhibit high levels of temporal operand value locality and operand value locality across SIMD lanes. Our implementation of the proposed masking scheme is augmented with the conventional pipeline logics. Simulation results verify that our scheme achieves up to 5.1% improvement in energy efficiency and 30% improvement in EDP (Energy-Delay-Product) over the baseline design.
AB - A significant amount of energy is consumed by a voltage guardband to ensure error-free operations under the worsening PVT variations in modern processors. Circuit-level timing speculation has become a popular approach that increases energy efficiency by removing such guardband and tolerating occasional timing errors. However, SIMD processors suffer from a large throughput and energy efficiency loss induced by a conventional error correction mechanism which requires several extra cycles for each timing error. In this paper, we present an error masking scheme to eliminate the chances of performing the error correction. The error masking is done by allowing potential erroneous addition instructions to reuse the partial result of previous operations. We show that reuse can be applied to a large number of addition instructions by exploiting the observations that SIMD applications exhibit high levels of temporal operand value locality and operand value locality across SIMD lanes. Our implementation of the proposed masking scheme is augmented with the conventional pipeline logics. Simulation results verify that our scheme achieves up to 5.1% improvement in energy efficiency and 30% improvement in EDP (Energy-Delay-Product) over the baseline design.
UR - http://www.scopus.com/inward/record.url?scp=84919683628&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2014.6974667
DO - 10.1109/ICCD.2014.6974667
M3 - Conference contribution
AN - SCOPUS:84919683628
T3 - 2014 32nd IEEE International Conference on Computer Design, ICCD 2014
SP - 90
EP - 96
BT - 2014 32nd IEEE International Conference on Computer Design, ICCD 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd IEEE International Conference on Computer Design, ICCD 2014
Y2 - 19 October 2014 through 22 October 2014
ER -