Abstract
A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task's memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor's voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18-88%.
| Original language | English |
|---|---|
| Article number | 371 |
| Journal | Micromachines |
| Volume | 10 |
| Issue number | 6 |
| DOIs | |
| State | Published - 1 Jun 2019 |
Bibliographical note
Funding Information:Funding: This research was funded by the ICT R & D program of MSIP/IITP (2019-0-00074, developing system software technologies for emerging new memory that adaptively learn workload characteristics) and also by the Basic Science Research Program through the NRF grant funded by Korea Government (MSIP) (No. 2019R1A2C1009275).
Publisher Copyright:
© 2019 by the authors.
Keywords
- Dynamic voltage scaling
- Low-power technique
- Nonvolatile memory
- Real-time system
- Task placement