Tight evaluation of real-time task schedulability for processor's DVS and nonvolatile memory allocation

Sunhwa A. Nam, Kyungwoon Cho, Hyokyung Bahn

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task's memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor's voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18-88%.

Original languageEnglish
Article number371
JournalMicromachines
Volume10
Issue number6
DOIs
StatePublished - 1 Jun 2019

Keywords

  • Dynamic voltage scaling
  • Low-power technique
  • Nonvolatile memory
  • Real-time system
  • Task placement

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