Phase-change memory (PCM) is a promising non-volatile memory technology that is anticipated to be used as main memory of computer systems in the not too far future. However, PCM has relatively long write latency and limited write endurance compared to DRAM. To mitigate these limitations of PCM, this paper presents a new last-level cache replacement policy that reduces the write traffic to PCM memory by considering the dirtiness of cache blocks when making a replacement decision. Specifically, the proposed policy tracks the dirtiness of a block at the granularity of a sub-block (i.e., cache line) and replaces a block with the least number of dirty sub-blocks among blocks not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 26% and 17% on average and up to 52% and 33% compared to NRU and RRIP, respectively, without performance degradations. It also extends the lifespan of PCM by 31% and reduces the energy consumption of PCM by 19% on average.