Temperature-Dependent Opacity of the Gate Field Inside MoS2 Field-Effect Transistors

Hyunjin Ji, Mohan Kumar Ghimire, Gwanmu Lee, Hojoon Yi, Wonkil Sakong, Hamza Zad Gul, Yoojoo Yun, Jinbao Jiang, Joonggyu Kim, Min Kyu Joo, Dongseok Suh, Seong Chu Lim

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

The transport behaviors of MoS2 field-effect transistors (FETs) with various channel thicknesses are studied. In a 12 nm thick MoS2 FET, a typical switching behavior is observed with an Ion/Ioff ratio of 106. However, in 70 nm thick MoS2 FETs, the gating effect weakens with a large off-current, resulting from the screening of the gate field by the carriers formed through the ionization of S vacancies at 300 K. Hence, when the latter is dual-gated, two independent conductions develop with different threshold voltage (VTH) and field-effect mobility (μFE) values. When the temperature is lowered for the latter, both the ionization of S vacancies and the gate-field screening reduce, which revives the strong Ion/Ioff ratio and merges the two separate channels into one. Thus, only one each of VTH and μFE are seen from the thick MoS2 FET when the temperature is less than 80 K. The change of the number of conduction channels is attributed to the ionization of S vacancies, which leads to a temperature-dependent intra- and interlayer conductance and the attenuation of the electrostatic gate field. The defect-related transport behavior of thick MoS2 enables us to propose a new device structure that can be further developed to a vertical inverter inside a single MoS2 flake.

Original languageEnglish
Pages (from-to)29022-29028
Number of pages7
JournalACS Applied Materials and Interfaces
Volume11
Issue number32
DOIs
StatePublished - 14 Aug 2019

Bibliographical note

Funding Information:
This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2019R1A2C1010742) of Korea and by IBS-R011-D1.

Publisher Copyright:
© 2019 American Chemical Society.

Keywords

  • dual-gated transistor
  • interlayer coupling
  • MoS
  • S vacancies
  • temperature-dependent gate-field attenuation

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