TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search

Ha Young Lim; Yeseo Jang; Juyeon Kim; Jaehyeong Sim

doi:10.1109/ISOCC59558.2023.10396202

TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search

Ha Young Lim, Yeseo Jang, Juyeon Kim, Jaehyeong Sim

Department of Computer Science & Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work presents TD-NAAS, a template-based differentiable approach towards the co-design of neural networks and hardware accelerator. Each neural operator is paired with the optimal hardware block that executes it efficiently, which is called a template. This approach reduces the search space by eliminating hardware design parameters and guarantees the most efficient accelerator. Evaluation results show that our method can build a neural network with higher accuracy and an accelerator with lower latency compared to the existing works.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2023, ISOCC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	143-144
Number of pages	2
ISBN (Electronic)	9798350327038
DOIs	https://doi.org/10.1109/ISOCC59558.2023.10396202
State	Published - 2023
Event	20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of Duration: 25 Oct 2023 → 28 Oct 2023

Publication series

Name	Proceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference	20th International SoC Design Conference, ISOCC 2023
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/23 → 28/10/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

HW/SW Co-Design
Neural Architecture Search

Access to Document

10.1109/ISOCC59558.2023.10396202

Cite this

Lim, H. Y., Jang, Y., Kim, J., & Sim, J. (2023). TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search. In Proceedings - International SoC Design Conference 2023, ISOCC 2023 (pp. 143-144). (Proceedings - International SoC Design Conference 2023, ISOCC 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC59558.2023.10396202

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title = "TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search",

abstract = "This work presents TD-NAAS, a template-based differentiable approach towards the co-design of neural networks and hardware accelerator. Each neural operator is paired with the optimal hardware block that executes it efficiently, which is called a template. This approach reduces the search space by eliminating hardware design parameters and guarantees the most efficient accelerator. Evaluation results show that our method can build a neural network with higher accuracy and an accelerator with lower latency compared to the existing works.",

keywords = "HW/SW Co-Design, Neural Architecture Search",

author = "Lim, {Ha Young} and Yeseo Jang and Juyeon Kim and Jaehyeong Sim",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 20th International SoC Design Conference, ISOCC 2023 ; Conference date: 25-10-2023 Through 28-10-2023",

year = "2023",

doi = "10.1109/ISOCC59558.2023.10396202",

language = "English",

series = "Proceedings - International SoC Design Conference 2023, ISOCC 2023",

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Lim, HY, Jang, Y, Kim, J & Sim, J 2023, TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search. in Proceedings - International SoC Design Conference 2023, ISOCC 2023. Proceedings - International SoC Design Conference 2023, ISOCC 2023, Institute of Electrical and Electronics Engineers Inc., pp. 143-144, 20th International SoC Design Conference, ISOCC 2023, Jeju, Korea, Republic of, 25/10/23. https://doi.org/10.1109/ISOCC59558.2023.10396202

TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search. / Lim, Ha Young; Jang, Yeseo; Kim, Juyeon et al.
Proceedings - International SoC Design Conference 2023, ISOCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 143-144 (Proceedings - International SoC Design Conference 2023, ISOCC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This work presents TD-NAAS, a template-based differentiable approach towards the co-design of neural networks and hardware accelerator. Each neural operator is paired with the optimal hardware block that executes it efficiently, which is called a template. This approach reduces the search space by eliminating hardware design parameters and guarantees the most efficient accelerator. Evaluation results show that our method can build a neural network with higher accuracy and an accelerator with lower latency compared to the existing works.

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BT - Proceedings - International SoC Design Conference 2023, ISOCC 2023

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 25 October 2023 through 28 October 2023

ER -

TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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Cite this