Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems

Bosung Jeon, Taejin Jang, Seongjae Cho, Hyungcheol Shin, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Essential characteristics of synapse arrays in neuromorphic systems include scalability, low-power operation, and precise vector-matrix multiplication (VMM). This paper investigates an asymmetric dual-gate synapse array that offers a power-efficient weight transfer method. By reconfiguring the arrangement of asymmetric gates, a 16 F2 cell-sized synapse array was produced. In addition, the array was fabricated with a buried-bottom gate structure, minimizing cell size and line resistance.

Original languageEnglish
Title of host publication2023 Silicon Nanoelectronics Workshop, SNW 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages15-16
Number of pages2
ISBN (Electronic)9784863488083
DOIs
StatePublished - 2023
Event26th Silicon Nanoelectronics Workshop, SNW 2023 - Kyoto, Japan
Duration: 11 Jun 202312 Jun 2023

Publication series

Name2023 Silicon Nanoelectronics Workshop, SNW 2023

Conference

Conference26th Silicon Nanoelectronics Workshop, SNW 2023
Country/TerritoryJapan
CityKyoto
Period11/06/2312/06/23

Bibliographical note

Publisher Copyright:
© 2023 JSAP.

Fingerprint

Dive into the research topics of 'Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems'. Together they form a unique fingerprint.

Cite this