Abstract
In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length (Lch) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current (Ioff) of 1.12 × 10-11 A/µm. In addition, the use of the high-k spacer dielectric HfO2 improves the on-state current (Ion) with an intrinsic delay time (τ) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower Ioff at a lower supply voltage (VDD) of 0.2 V.
| Original language | English |
|---|---|
| Pages (from-to) | 172-178 |
| Number of pages | 7 |
| Journal | Journal of Semiconductor Technology and Science |
| Volume | 16 |
| Issue number | 2 |
| DOIs | |
| State | Published - Apr 2016 |
Bibliographical note
Funding Information:This work was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) under Grants 2013-011522 and in part by Samsung Electronics Corporation. This work was also supported by Global Ph.D. Fellowship Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2013H1A2A1034363).
Publisher Copyright:
© 2016, Institute of Electronics Engineers of Korea. All rights reserved.
Keywords
- Ge/GaAs heterojunction
- Low-power (LP) performance
- Short-channel effect (SCE)
- Tunneling field-effect transistor (TFET)
- Vertical tunneling operation