Stress management in sub-90-nm transistor architecture

R. Arghavani, Z. Yuan, N. Ingle, K. B. Jung, M. Seamons, S. Venkataraman, V. Banthia, K. Lilja, P. Leon, G. Karunasiri, S. Yoon, A. Mascarenhas

Research output: Contribution to journalArticlepeer-review

42 Scopus citations


This brief focuses on the physical characteristics of three dielectric films which can induce a significant degree of tensile or compressive stress in the channel of a sub-90-nm node MOS structure. Manufacturable and highly reliable oxide films have demonstrated, based on simulation, the ability to induce greater than 1.5-GPa tensile stress in the Si channel, when used as shallow trench isolation (STI) fill. Low-temperature blanket nitride films with a stress range of 2 GPa compressive to greater than 1.4 GPa tensile were also developed to enhance performance in both PMOS and NMOS devices. Combined with a tensile first interlayer dielectric film, the stress management and optimization of the above films can yield significant performance improvement without additional cost, or integration complexities.

Original languageEnglish
Pages (from-to)1740-1743
Number of pages4
JournalIEEE Transactions on Electron Devices
Issue number10
StatePublished - Oct 2004


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