Abstract
A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.
Original language | English |
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Pages (from-to) | 42-46 |
Number of pages | 5 |
Journal | Solid-State Electronics |
Volume | 64 |
Issue number | 1 |
DOIs | |
State | Published - Oct 2011 |
Keywords
- 3D NAND flash memory
- Stacked-nanowires
- Virtual source/drain