Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory

Won Bo Shim, Seongjae Cho, Jung Hoon Lee, Dong Hua Li, Doo Hyun Kim, Gil Sung Lee, Yoon Kim, Se Hwan Park, Wandong Kim, Jungdal Choi, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

Original languageEnglish
Article number6081945
Pages (from-to)307-313
Number of pages7
JournalIEEE Transactions on Nanotechnology
Issue number2
StatePublished - Mar 2012

Bibliographical note

Funding Information:
Manuscript received November 7, 2010; revised February 7, 2011, May 26, 2011, and August 10, 2011; accepted October 6, 2011. Date of publication November 15, 2011; date of current version March 9, 2012. This work was supported by Samsung Electronics Corporation under a project entitled with “Development of SONOS Flash Memory Device for Very Large Scale Integration (VLSI).” The review of this paper was arranged by Associate Editor M. M. De Souza.


  • 3-D NAND flash memory
  • Cut-off gate
  • stacked gated twin-bit (SGTB)
  • vertical channel


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