Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory

Won Bo Shim; Seongjae Cho; Jung Hoon Lee; Dong Hua Li; Doo Hyun Kim; Gil Sung Lee; Yoon Kim; Se Hwan Park; Wandong Kim; Jungdal Choi; Byung Gook Park

doi:10.1109/TNANO.2011.2172217

Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory

Won Bo Shim, Seongjae Cho, Jung Hoon Lee, Dong Hua Li, Doo Hyun Kim, Gil Sung Lee, Yoon Kim, Se Hwan Park, Wandong Kim, Jungdal Choi, Byung Gook Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

Original language	English
Article number	6081945
Pages (from-to)	307-313
Number of pages	7
Journal	IEEE Transactions on Nanotechnology
Volume	11
Issue number	2
DOIs	https://doi.org/10.1109/TNANO.2011.2172217
State	Published - Mar 2012

Bibliographical note

Funding Information:
Manuscript received November 7, 2010; revised February 7, 2011, May 26, 2011, and August 10, 2011; accepted October 6, 2011. Date of publication November 15, 2011; date of current version March 9, 2012. This work was supported by Samsung Electronics Corporation under a project entitled with “Development of SONOS Flash Memory Device for Very Large Scale Integration (VLSI).” The review of this paper was arranged by Associate Editor M. M. De Souza.

Keywords

3-D NAND flash memory
Cut-off gate
SONOS
stacked gated twin-bit (SGTB)
vertical channel

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10.1109/TNANO.2011.2172217

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@article{b7740ad322e84fa2b8b9c4304adda06a,

title = "Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory",

abstract = "A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.",

keywords = "3-D NAND flash memory, Cut-off gate, SONOS, stacked gated twin-bit (SGTB), vertical channel",

author = "Shim, {Won Bo} and Seongjae Cho and Lee, {Jung Hoon} and Li, {Dong Hua} and Kim, {Doo Hyun} and Lee, {Gil Sung} and Yoon Kim and Park, {Se Hwan} and Wandong Kim and Jungdal Choi and Park, {Byung Gook}",

note = "Funding Information: Manuscript received November 7, 2010; revised February 7, 2011, May 26, 2011, and August 10, 2011; accepted October 6, 2011. Date of publication November 15, 2011; date of current version March 9, 2012. This work was supported by Samsung Electronics Corporation under a project entitled with “Development of SONOS Flash Memory Device for Very Large Scale Integration (VLSI).” The review of this paper was arranged by Associate Editor M. M. De Souza.",

year = "2012",

month = mar,

doi = "10.1109/TNANO.2011.2172217",

language = "English",

volume = "11",

pages = "307--313",

journal = "IEEE Transactions on Nanotechnology",

issn = "1536-125X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory

AU - Shim, Won Bo

AU - Cho, Seongjae

AU - Lee, Jung Hoon

AU - Li, Dong Hua

AU - Kim, Doo Hyun

AU - Lee, Gil Sung

AU - Kim, Yoon

AU - Park, Se Hwan

AU - Kim, Wandong

AU - Choi, Jungdal

AU - Park, Byung Gook

N1 - Funding Information: Manuscript received November 7, 2010; revised February 7, 2011, May 26, 2011, and August 10, 2011; accepted October 6, 2011. Date of publication November 15, 2011; date of current version March 9, 2012. This work was supported by Samsung Electronics Corporation under a project entitled with “Development of SONOS Flash Memory Device for Very Large Scale Integration (VLSI).” The review of this paper was arranged by Associate Editor M. M. De Souza.

PY - 2012/3

Y1 - 2012/3

N2 - A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

AB - A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

KW - 3-D NAND flash memory

KW - Cut-off gate

KW - SONOS

KW - stacked gated twin-bit (SGTB)

KW - vertical channel

UR - http://www.scopus.com/inward/record.url?scp=84863379196&partnerID=8YFLogxK

U2 - 10.1109/TNANO.2011.2172217

DO - 10.1109/TNANO.2011.2172217

M3 - Article

AN - SCOPUS:84863379196

SN - 1536-125X

VL - 11

SP - 307

EP - 313

JO - IEEE Transactions on Nanotechnology

JF - IEEE Transactions on Nanotechnology

IS - 2

M1 - 6081945

ER -

Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory

Abstract

Bibliographical note

Keywords

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