@article{b7740ad322e84fa2b8b9c4304adda06a,
title = "Stacked gated twin-bit (SGTB) SONOS memory device for high-density flash memory",
abstract = "A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.",
keywords = "3-D NAND flash memory, Cut-off gate, SONOS, stacked gated twin-bit (SGTB), vertical channel",
author = "Shim, {Won Bo} and Seongjae Cho and Lee, {Jung Hoon} and Li, {Dong Hua} and Kim, {Doo Hyun} and Lee, {Gil Sung} and Yoon Kim and Park, {Se Hwan} and Wandong Kim and Jungdal Choi and Park, {Byung Gook}",
note = "Funding Information: Manuscript received November 7, 2010; revised February 7, 2011, May 26, 2011, and August 10, 2011; accepted October 6, 2011. Date of publication November 15, 2011; date of current version March 9, 2012. This work was supported by Samsung Electronics Corporation under a project entitled with “Development of SONOS Flash Memory Device for Very Large Scale Integration (VLSI).” The review of this paper was arranged by Associate Editor M. M. De Souza.",
year = "2012",
month = mar,
doi = "10.1109/TNANO.2011.2172217",
language = "English",
volume = "11",
pages = "307--313",
journal = "IEEE Transactions on Nanotechnology",
issn = "1536-125X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",
}