Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation

Soomin Kim; Seeun Oh; Md Hasan Raza Ansari; Nazek El-Atab; Seongjae Cho

doi:10.1109/ICCE-Asia59966.2023.10326399

Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation

Soomin Kim, Seeun Oh, Md Hasan Raza Ansari, Nazek El-Atab, Seongjae Cho

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, a novel single-body-integrated complementary tunneling field-effect transistor (SBI CTFET) is proposed and optimally designed by series of rigorous device simulations. The proposed device demonstrates both n-type and p-type enhancement operations free from the ambipolar characteristics of a TFET sharing the channel in common, enabling highly reliable operations and plausibly scaled cell area. The subthreshold swing (S) values for n-type and p-type in the single cell were 55 mV/dec. Moreover, the processing margin in forming its dual gates is systematically suggested for future designers.

Original language	English
Title of host publication	2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350344318
DOIs	https://doi.org/10.1109/ICCE-Asia59966.2023.10326399
State	Published - 2023
Event	2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023 - Busan, Korea, Republic of Duration: 23 Oct 2023 → 25 Oct 2023

Publication series

Name	2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023

Conference

Conference	2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023
Country/Territory	Korea, Republic of
City	Busan
Period	23/10/23 → 25/10/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

area scaling
complementary tunneling field-effect transistor
enhancement mode
processing margin
reliable operation
single-body-integration

Access to Document

10.1109/ICCE-Asia59966.2023.10326399

Cite this

Kim, S., Oh, S., Ansari, M. H. R., El-Atab, N., & Cho, S. (2023). Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation. In 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023 (2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE-Asia59966.2023.10326399

Kim, Soomin ; Oh, Seeun ; Ansari, Md Hasan Raza et al. / Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation. 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023).

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abstract = "In this work, a novel single-body-integrated complementary tunneling field-effect transistor (SBI CTFET) is proposed and optimally designed by series of rigorous device simulations. The proposed device demonstrates both n-type and p-type enhancement operations free from the ambipolar characteristics of a TFET sharing the channel in common, enabling highly reliable operations and plausibly scaled cell area. The subthreshold swing (S) values for n-type and p-type in the single cell were 55 mV/dec. Moreover, the processing margin in forming its dual gates is systematically suggested for future designers.",

keywords = "area scaling, complementary tunneling field-effect transistor, enhancement mode, processing margin, reliable operation, single-body-integration",

author = "Soomin Kim and Seeun Oh and Ansari, \{Md Hasan Raza\} and Nazek El-Atab and Seongjae Cho",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023 ; Conference date: 23-10-2023 Through 25-10-2023",

year = "2023",

doi = "10.1109/ICCE-Asia59966.2023.10326399",

language = "English",

series = "2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023",

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Kim, S, Oh, S, Ansari, MHR, El-Atab, N & Cho, S 2023, Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation. in 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023. 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023, Busan, Korea, Republic of, 23/10/23. https://doi.org/10.1109/ICCE-Asia59966.2023.10326399

Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation. / Kim, Soomin; Oh, Seeun; Ansari, Md Hasan Raza et al.
2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - El-Atab, Nazek

AU - Cho, Seongjae

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Y1 - 2023

N2 - In this work, a novel single-body-integrated complementary tunneling field-effect transistor (SBI CTFET) is proposed and optimally designed by series of rigorous device simulations. The proposed device demonstrates both n-type and p-type enhancement operations free from the ambipolar characteristics of a TFET sharing the channel in common, enabling highly reliable operations and plausibly scaled cell area. The subthreshold swing (S) values for n-type and p-type in the single cell were 55 mV/dec. Moreover, the processing margin in forming its dual gates is systematically suggested for future designers.

AB - In this work, a novel single-body-integrated complementary tunneling field-effect transistor (SBI CTFET) is proposed and optimally designed by series of rigorous device simulations. The proposed device demonstrates both n-type and p-type enhancement operations free from the ambipolar characteristics of a TFET sharing the channel in common, enabling highly reliable operations and plausibly scaled cell area. The subthreshold swing (S) values for n-type and p-type in the single cell were 55 mV/dec. Moreover, the processing margin in forming its dual gates is systematically suggested for future designers.

KW - area scaling

KW - complementary tunneling field-effect transistor

KW - enhancement mode

KW - processing margin

KW - reliable operation

KW - single-body-integration

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U2 - 10.1109/ICCE-Asia59966.2023.10326399

DO - 10.1109/ICCE-Asia59966.2023.10326399

M3 - Conference contribution

AN - SCOPUS:85179883236

T3 - 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023

BT - 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023

Y2 - 23 October 2023 through 25 October 2023

ER -

Kim S, Oh S, Ansari MHR, El-Atab N, Cho S. Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation. In 2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2023). doi: 10.1109/ICCE-Asia59966.2023.10326399

Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation

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