Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

Jae Sung Lee, Jae Hwa Seo, Seongjae Cho, Jung Hee Lee, Shin Won Kang, Jin Hyuk Bae, Eou Sik Cho, In Man Kang

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In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (Ion), off-current (Ioff), subthreshold swing (S), and Ion/Ioff ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (fT) and maximum oscillation frequency (f max) on gate-drain capacitance (Cgd) with the underlapping were investigated as the gate length (Lgate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.

Original languageEnglish
Pages (from-to)1143-1149
Number of pages7
JournalCurrent Applied Physics
Issue number6
StatePublished - Aug 2013

Bibliographical note

Funding Information:
This research was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Korean Ministry of Education, Science and Technology (MEST) under Grants 2011-0025701 , 2012-0005671 and 2012-0000619 , in part by Samsung Electronics Corporation. Dr. S. Cho was supported by the NRF Grant funded by the Korean Government ( NRF-2011-357-D00155 ).


  • Asymmetric junctions
  • Drain underlap
  • Gate-all-around (GAA)
  • Radio-frequency (RF)
  • Tunneling field-effect transistor (TFET)


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