Simulation for silicon-compatible InGaAs-based junctionless field-effect transistor using InP buffer layer

In this paper, we present the optimized performances of indium gallium arsenide (InGaAs)-based compound junctionless field-effect transistors (JLFETs) using an indium phosphide (InP) buffer layer. The proposed InGaAs-InP material combination with little lattice mismatch provides a significant improvement in current drivability securing various potential applications. Device optimization is performed in terms of primary dc parameters and characterization is investigated by two-dimensional (2D) technology computer-aided design simulations. The optimization variables were the channel doping concentration (N_ch), the buffer doping concentration (N_bf), and the channel thickness (T_ch). For the optimally designed InGaAs JLFET, on-state current (I_on) of 325 μA μm^-1, subthreshold swing (S) of 80 mV dec^-1, and current ratio (I_on/I _off) of 10⁹ were obtained. In the end, the results are compared with the data of silicon (Si)-based JL MOSFETs to confirm the improvements.