This paper presents a CMOS-compatible process for fabrication of 3D structures embedded in the volume of a silicon wafer, and capable of interconnection to circuitry on the wafer surface. The key challenge of embedding structures in the silicon substrate is processing inside deep silicon trenches. This difficulty is overcome by means of several key techniques: multilevel wafer etching; cavity shaping; fine proximity lithography at the bottom of trenches; and laminated dry-film lithography on complex 3D structures. As a technology demonstration, a topologically complex 3D toroidal inductor is fabricated in a deep silicon trench, and is coupled to the wafer surface with high-power, electroplated through-wafer interconnect. Inductors fabricated in these trenches achieved an overall inductance of 60 nH, dc resistance of 399 MΩ, and quality factor of 17.5 at 70 MHz.