Short-channel tunneling field-effect transistor with drain-overlap and dual-metal gate structure for low-power and high-speed operations

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (C_gd) because of the increase in the overlap capacitance (C_ov) and inversion capacitance (C_inv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (C_gg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φ_overlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower C_gg divided by the on-state current (I_on), i.e., C_gg/I_on. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.