Scaling the MOS transistor to its limit in ULSI

A. F. Tasch, H. Shin

Research output: Contribution to journalConference articlepeer-review


The history and progress in MOS integrated circuit technology since the mid 1960's has been dominated by the scaling of feature size. Minimum feature size has decreased from around 25 microns in the mid 1960's to 0.8 microns in the latest state-of-the-art products today. This progress along with other technological advances has increased the level of integration from a approx. 100 transistors per chip to over 4 × 106 transistors per chip in the latest products today. The economic and technological advantages of feature size scaling were recognized early, and the first methodology for self-consistent scaling was proposed by Dennard et al. in 1974. This methodology offered new insight to scaling of both the MOS transistor and the other circuit elements, and it was based on maintaining a constant maximum electric field in the MOS transistor. Recent progress is summarized, heading from the conventional MOSFET to the LDD MOSFET. A new hot-carrier-suppressed MOSFET structure is reported.

Original languageEnglish
Pages (from-to)3-11
Number of pages9
JournalProceedings - The Electrochemical Society
Issue number7
StatePublished - 1990
EventProceedings of the Sixth International Symposium on Silicon Materials Science and Technology - Montreal, Que, Can
Duration: 7 May 199011 May 1990


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