Quantum effects in CMOS devices

Keun Jeong Lee, Ji Sun Park, Hyungsoon Shin

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


A MOSFET device is scaled to the deep sub-micron region in advanced VLSI system technology. If the short-channel effect is to be reduced and the device performance maximized in such device, the oxide thickness should be reduced and the substrate doping should be increased. As a result, a potential well is formed at the Si/SiO2 interface, and a quantum effect occurs In this work, a new simulator, which predicts the quantum and the poly-depletion effects in a MOSFET structure, is developed. Using a self-consistent method, this simulator accurately predicts the carrier distribution because the calculation of the potential in the inversion layer is improved. Using the developed simulator, we compare the quantum effects in NMOS and PMOS, and analyze the differences. The oxide thickness and the channel doping dependences of the quantum effect are analyzed, and their causes are investigated. Also, buried-channel and surface-channel devices are compared, and the differences and causes of the differences are analyzed.

Original languageEnglish
Pages (from-to)902-907
Number of pages6
JournalJournal of the Korean Physical Society
Issue number6
StatePublished - Dec 2002


  • Buried PMOS
  • Capacitance reduction threshold voltage increment
  • NMOS
  • PMOS
  • Poly-depletion effect
  • Quantum effect
  • Self-consistent mothod


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