TY - GEN
T1 - Post-Quantum Cryptography Coprocessor for RISC-V CPU Core
AU - Lee, Jihye
AU - Kim, Whijin
AU - Kim, Sohyeon
AU - Kim, Ji Hoon
N1 - Funding Information:
This research was supported by Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government(MSIT) (No. 2020‐ 0 ‐ 01308, Intelligent Mobile Processor based on Deep-Learning Micro Core Array)
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The importance of PQC (Post-Quantum Cryptography) is highly emphasized according to the advancement of quantum computing technology and emergence of Shor's algorithm. Various PQC algorithms are developed but their high computational complexity makes implementation challenging. Dedicated hardware accelerator lacks flexibility to new algorithms and software implementation requires high execution time. We propose a PQC coprocessor with RISC-V ISA(Instruction Set Architecture) extension supporting not only round-3 candidates in NIST(National Institute of Standards and Technology) PQC standardization process including CRYSTALS-KYBER, CRYSTALS-DILITHIUM, FrodoKEM, SABER, NTRU and Falcon, but also upcoming new algorithms. Proposed architecture supports Keccak, NTT (Number Theoretic Transform), sampling and arithmetic operations including conditional addition and subtraction. The proposed PQC ISA extension includes RISC-V scalar cryptography and bit-manipulation extension. The coprocessor can be attached to baseline RISC-V CPU core through coprocessor interface. PQC instruction considered invalid by CPU core is offloaded through coprocessor interface.
AB - The importance of PQC (Post-Quantum Cryptography) is highly emphasized according to the advancement of quantum computing technology and emergence of Shor's algorithm. Various PQC algorithms are developed but their high computational complexity makes implementation challenging. Dedicated hardware accelerator lacks flexibility to new algorithms and software implementation requires high execution time. We propose a PQC coprocessor with RISC-V ISA(Instruction Set Architecture) extension supporting not only round-3 candidates in NIST(National Institute of Standards and Technology) PQC standardization process including CRYSTALS-KYBER, CRYSTALS-DILITHIUM, FrodoKEM, SABER, NTRU and Falcon, but also upcoming new algorithms. Proposed architecture supports Keccak, NTT (Number Theoretic Transform), sampling and arithmetic operations including conditional addition and subtraction. The proposed PQC ISA extension includes RISC-V scalar cryptography and bit-manipulation extension. The coprocessor can be attached to baseline RISC-V CPU core through coprocessor interface. PQC instruction considered invalid by CPU core is offloaded through coprocessor interface.
KW - Post-quantum cryptography
KW - RISC-V
UR - http://www.scopus.com/inward/record.url?scp=85128837110&partnerID=8YFLogxK
U2 - 10.1109/ICEIC54506.2022.9748834
DO - 10.1109/ICEIC54506.2022.9748834
M3 - Conference contribution
AN - SCOPUS:85128837110
T3 - 2022 International Conference on Electronics, Information, and Communication, ICEIC 2022
BT - 2022 International Conference on Electronics, Information, and Communication, ICEIC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 6 February 2022 through 9 February 2022
ER -