Performance Improvement of 1T DRAM by Raised Source and Drain Engineering

Md Hasan Raza Ansari, Seongjae Cho

Research output: Contribution to journalArticlepeer-review

17 Scopus citations

Abstract

In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time ( {T}-{text {ret}} ) and larger sensing margin (SM). The designed 1T DRAM achieves {T}-{text {ret}} sim {330} and sim 200 ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write '1') and energy ( 2.16times 10{-15} J for read '1' and 1.5times 10{-17} J for read '0' operations). Furthermore, it is revealed that low-kappa spacer has an effect of increasing {T}-{text {ret}} in the device.

Original languageEnglish
Article number9354433
Pages (from-to)1577-1584
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume68
Issue number4
DOIs
StatePublished - Apr 2021

Bibliographical note

Funding Information:
Manuscript received January 4, 2021; accepted January 31, 2021. Date of publication February 15, 2021; date of current version March 24, 2021. This work was supported in part by the Ministry of Trade, Industry and Energy (MOTIE), in part by the Korea Semiconductor Research Consortium (KSRC) support Program for the development of future semiconductor devices under Grant 10080513, and in part by the IC Design Education Center (IDEC) Program. The review of this article was arranged by Editor P.-Y. Du. (Corresponding author: Seongjae Cho.) The authors are with the Department of Electronic Engineering, Gachon University, Seongnam-si 13120, South Korea, and also with the Graduate School of IT Convergence Engineering, Gachon University, Seongnam-si 13120, South Korea (e-mail: felixcho@gachon.ac.kr).

Publisher Copyright:
© 1963-2012 IEEE.

Keywords

  • Double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET)
  • low-power operation
  • one-transistor (1T) dynamic random access memory (DRAM)
  • retention time
  • sensing margin (SM)
  • technology computer-aided design (TCAD)

Fingerprint

Dive into the research topics of 'Performance Improvement of 1T DRAM by Raised Source and Drain Engineering'. Together they form a unique fingerprint.

Cite this