P-Channel nonvolatile flash memory with a dopant-segregated schottky-barrier source/drain

Sung Jin Choi; Jin Woo Han; Dong Il Moon; Sungho Kim; Moongyu Jang; Yang Kyu Choi

doi:10.1109/TED.2010.2051331

P-Channel nonvolatile flash memory with a dopant-segregated schottky-barrier source/drain

Sung Jin Choi, Jin Woo Han, Dong Il Moon, Sungho Kim, Moongyu Jang, Yang Kyu Choi

Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 μs.

Original language	English
Article number	5497127
Pages (from-to)	1737-1742
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	57
Issue number	8
DOIs	https://doi.org/10.1109/TED.2010.2051331
State	Published - Aug 2010

Keywords

Bit-by-bit
dopant-segregation (DS)
FINFET
flash memory
multilevel cell (MLC)
NAND flash
nickel
nickel silicidation
Nisi
nonvolatile memory
p-channel
Schottky-barrier
Schottky-barrier MOSFET
silicon-oxidenitride-oxide-silicon (SONOS)
V control

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10.1109/TED.2010.2051331

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title = "P-Channel nonvolatile flash memory with a dopant-segregated schottky-barrier source/drain",

abstract = "A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 μs.",

keywords = "Bit-by-bit, dopant-segregation (DS), FINFET, flash memory, multilevel cell (MLC), NAND flash, nickel, nickel silicidation, Nisi, nonvolatile memory, p-channel, Schottky-barrier, Schottky-barrier MOSFET, silicon-oxidenitride-oxide-silicon (SONOS), V control",

author = "Choi, {Sung Jin} and Han, {Jin Woo} and Moon, {Dong Il} and Sungho Kim and Moongyu Jang and Choi, {Yang Kyu}",

year = "2010",

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doi = "10.1109/TED.2010.2051331",

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T1 - P-Channel nonvolatile flash memory with a dopant-segregated schottky-barrier source/drain

AU - Choi, Sung Jin

AU - Han, Jin Woo

AU - Moon, Dong Il

AU - Kim, Sungho

AU - Jang, Moongyu

AU - Choi, Yang Kyu

PY - 2010/8

Y1 - 2010/8

N2 - A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 μs.

AB - A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 μs.

KW - Bit-by-bit

KW - dopant-segregation (DS)

KW - FINFET

KW - flash memory

KW - multilevel cell (MLC)

KW - NAND flash

KW - nickel

KW - nickel silicidation

KW - Nisi

KW - nonvolatile memory

KW - p-channel

KW - Schottky-barrier

KW - Schottky-barrier MOSFET

KW - silicon-oxidenitride-oxide-silicon (SONOS)

KW - V control

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

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M1 - 5497127

ER -

P-Channel nonvolatile flash memory with a dopant-segregated schottky-barrier source/drain

Abstract

Keywords

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