Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

Chaewon Yun; Sangwan Kim; Seongjae Cho; Il Hwan Cho; Hyunwoo Kim; Jang Hyun Kim; Garam Kim

doi:10.5573/JSTS.2023.23.4.207

Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

Chaewon Yun, Sangwan Kim, Seongjae Cho, Il Hwan Cho, Hyunwoo Kim, Jang Hyun Kim, Garam Kim

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (I_ON) can be increased by highly localized point tunneling while suppressing off-current (I_OFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (I_ON/I_OFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm.

Original language	English
Pages (from-to)	207-214
Number of pages	8
Journal	Journal of Semiconductor Technology and Science
Volume	23
Issue number	4
DOIs	https://doi.org/10.5573/JSTS.2023.23.4.207
State	Published - Aug 2023

Bibliographical note

Publisher Copyright:
© 2023, Institute of Electronics Engineers of Korea. All rights reserved.

Keywords

Dual workfunction
TCAD device simulation
junction underlap
line tunneling field-effect transistor (LTFET)
low-power operation

Access to Document

10.5573/JSTS.2023.23.4.207

Cite this

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title = "Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction",

abstract = "In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm.",

keywords = "Dual workfunction, TCAD device simulation, junction underlap, line tunneling field-effect transistor (LTFET), low-power operation",

author = "Chaewon Yun and Sangwan Kim and Seongjae Cho and Cho, {Il Hwan} and Hyunwoo Kim and Kim, {Jang Hyun} and Garam Kim",

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AU - Yun, Chaewon

AU - Kim, Sangwan

AU - Cho, Seongjae

AU - Cho, Il Hwan

AU - Kim, Hyunwoo

AU - Kim, Jang Hyun

AU - Kim, Garam

PY - 2023/8

Y1 - 2023/8

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AB - In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm.

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KW - TCAD device simulation

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Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

Abstract

Bibliographical note

Keywords

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