Ni/GeOx/p+ Si resistive-switching random-access memory with full Si processing compatibility and its characterization and modeling

Jae Yoon Lee, Youngmin Kim, Min Hwi Kim, Seoyeon Go, Seung Wook Ryu, Jae Yeon Lee, Tae Jung Ha, Soo Gil Kim, Seongjae Cho, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

In this study, a fully Si-compatible resistive-switching random-access memory (ReRAM) employing GeOx as the switching layer is fabricated, analyzed, and characterized. I–V curves and endurance characteristics have been obtained from the measurement of fabricated GeOx ReRAM devices. From the measurement results, the size dependence of the operation voltages is investigated. Here, we have carefully prepared the methods for GeOx switching layer and its interfaces. Physical vapor deposition (PVD) by an evaporator and subsequent thermal oxidation are the key processes for the switching layer. Additional annealing was performed and its effects on device performances have been closely investigated. It was revealed from the measurement results that the forming voltage of the GeOx ReRAM cell was lower than set voltage. This merit of forming-freeness gets rid of the necessity of preparing an additional voltage scheme and relatively complicated peripheral circuit for generating the forming voltage which is the highest value among the operation voltages in most cases. The low-resistance state (LRS) and high-resistance state (HRS) current ratio is larger than 103 and the number of endurance cycles reaches 400 even under the harsh condition of DC sweep mode. At the end of this study, a DC compact model for the fabricated ReRAM cell is schemed intuitively by simple elements including variable resistors, capacitors, and switches. The components in the conceived model are allowed to have highly accurate values by figuring out the predominant conduction mechanism and comparing with the measurement results in the recursive manner. The systematic study embracing process architecture, device fabrication and characterization, and circuit modeling would be highly beneficial in the array and system level architecture design.

Original languageEnglish
Pages (from-to)63-70
Number of pages8
JournalVacuum
Volume161
DOIs
StatePublished - Mar 2019

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© 2018

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