Nanosculpture: Three-dimensional CMOS device structures for the ULSI era

Byung Gook Park; Jae Young Song; Jong Pil Kim; Hoon Jeong; Jung Hoon Lee; Seongjae Cho

doi:10.1016/j.mejo.2008.11.011

Nanosculpture: Three-dimensional CMOS device structures for the ULSI era

Byung Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide-nitride-oxide-silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density.

Original language	English
Pages (from-to)	769-772
Number of pages	4
Journal	Microelectronics Journal
Volume	40
Issue number	4-5
DOIs	https://doi.org/10.1016/j.mejo.2008.11.011
State	Published - Apr 2009

Bibliographical note

Funding Information:
This work was supported by the Ministry of Science and Technology through the Tera-bit Level Nano Device Project, and by Samsung Electronics Corporation through the cooperative project “Research on Structure and Characterization of the Nonvolatile Memory Devices.”

Keywords

Charge trap flash memory
CMOS scaling
Three-dimensional MOSFET

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10.1016/j.mejo.2008.11.011

Cite this

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title = "Nanosculpture: Three-dimensional CMOS device structures for the ULSI era",

abstract = "CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide-nitride-oxide-silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density.",

keywords = "Charge trap flash memory, CMOS scaling, Three-dimensional MOSFET",

author = "Park, {Byung Gook} and Song, {Jae Young} and Kim, {Jong Pil} and Hoon Jeong and Lee, {Jung Hoon} and Seongjae Cho",

note = "Funding Information: This work was supported by the Ministry of Science and Technology through the Tera-bit Level Nano Device Project, and by Samsung Electronics Corporation through the cooperative project “Research on Structure and Characterization of the Nonvolatile Memory Devices.”",

year = "2009",

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doi = "10.1016/j.mejo.2008.11.011",

language = "English",

volume = "40",

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AU - Song, Jae Young

AU - Kim, Jong Pil

AU - Jeong, Hoon

AU - Lee, Jung Hoon

AU - Cho, Seongjae

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PY - 2009/4

Y1 - 2009/4

N2 - CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide-nitride-oxide-silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density.

AB - CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide-nitride-oxide-silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density.

KW - Charge trap flash memory

KW - CMOS scaling

KW - Three-dimensional MOSFET

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JF - Microelectronics Journal

IS - 4-5

ER -

Nanosculpture: Three-dimensional CMOS device structures for the ULSI era

Abstract

Bibliographical note

Keywords

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