Nanosculpture: Three-dimensional CMOS device structures for the ULSI era

Byung Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide-nitride-oxide-silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density.

Original languageEnglish
Pages (from-to)769-772
Number of pages4
JournalMicroelectronics Journal
Issue number4-5
StatePublished - Apr 2009

Bibliographical note

Funding Information:
This work was supported by the Ministry of Science and Technology through the Tera-bit Level Nano Device Project, and by Samsung Electronics Corporation through the cooperative project “Research on Structure and Characterization of the Nonvolatile Memory Devices.”


  • Charge trap flash memory
  • CMOS scaling
  • Three-dimensional MOSFET


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