Multiple-gate CMOS thin-film ransistor with polysilicon nanowire

Maesoon Im; Jim Woo Han; Hyunjin Lee; Lee Eun Yu; Sungho Kim; Chang Hoon Kim; Sang Cheol Jeon; Kwang Hee Kim; Gi Sung Lee; Jae Sub Oh; Yun Chang Park; Hee Mok Lee; Yang Kyu Choi

doi:10.1109/LED.2007.911982

Multiple-gate CMOS thin-film ransistor with polysilicon nanowire

Maesoon Im, Jim Woo Han, Hyunjin Lee, Lee Eun Yu, Sungho Kim, Chang Hoon Kim, Sang Cheol Jeon, Kwang Hee Kim, Gi Sung Lee, Jae Sub Oh, Yun Chang Park, Hee Mok Lee, Yang Kyu Choi

Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

64 Scopus citations

Abstract

An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.

Original language	English
Pages (from-to)	102-105
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	29
Issue number	1
DOIs	https://doi.org/10.1109/LED.2007.911982
State	Published - Jan 2008

Keywords

CMOS
Multiple gate
Nanoscale
Nanowire
Thin-film transistor (TFT)
Vertical integration

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10.1109/LED.2007.911982

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abstract = "An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.",

keywords = "CMOS, Multiple gate, Nanoscale, Nanowire, Thin-film transistor (TFT), Vertical integration",

author = "Maesoon Im and Han, {Jim Woo} and Hyunjin Lee and Yu, {Lee Eun} and Sungho Kim and Kim, {Chang Hoon} and Jeon, {Sang Cheol} and Kim, {Kwang Hee} and Lee, {Gi Sung} and Oh, {Jae Sub} and Park, {Yun Chang} and Lee, {Hee Mok} and Choi, {Yang Kyu}",

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AU - Im, Maesoon

AU - Han, Jim Woo

AU - Lee, Hyunjin

AU - Yu, Lee Eun

AU - Kim, Sungho

AU - Kim, Chang Hoon

AU - Jeon, Sang Cheol

AU - Kim, Kwang Hee

AU - Lee, Gi Sung

AU - Oh, Jae Sub

AU - Park, Yun Chang

AU - Lee, Hee Mok

AU - Choi, Yang Kyu

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AB - An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.

KW - CMOS

KW - Multiple gate

KW - Nanoscale

KW - Nanowire

KW - Thin-film transistor (TFT)

KW - Vertical integration

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Multiple-gate CMOS thin-film ransistor with polysilicon nanowire

Abstract

Keywords

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