@article{b3559f8c9c1e494a8f392164ca49b8cd,
title = "Multilevel switching characteristics of Si3N4-based nano-wedge resistive switching memory and array simulation for in-memory computing application",
abstract = "In this research, nano-wedge resistive switching random-access memory (ReRAM) based on a Si3N4 switching layer and silicon bottom electrode was fabricated, and its multilevel switching characteristics were investigated. The wedge bottom electrode was formed by a tetramethyl ammonium hydroxide (TMAH) wet-etching process. The nano-wedge ReRAM was demonstrated to have different reset current levels by varying the compliance currents. To explain the effect of modulating the compliance currents, the switching characteristics of both the SET and RESET behaviors were shown. After measuring the device under four different compliance currents, it was proved to have different current levels due to an inhibited resistive state after a SET switching process. Furthermore, SPICE circuit simulation was carried out to show the effect of line resistance on current summation for the array sizes of 8 × 8 and 16 × 16. These results indicate the importance of minimizing the line resistance for successful implementation as a hardware-based neural network.",
keywords = "Array, Nano-wedge, Neural network, Resistive switching random-access memory, Switching layer, Switching process, TMAH",
author = "Lee, {Dong Keun} and Kim, {Min Hwi} and Suhyun Bang and Kim, {Tae Hyeon} and Sungjun Kim and Seongjae Cho and Park, {Byung Gook}",
note = "Funding Information: 4.ConclusionsFor an in-depth analysis of the effect of bit line (BL) resistance on the read current of individual array cells, a simulation was carried out to demonstrate the loss of cell3cu4rrent, as depicted in Figure 9. In Figure 9a, the simulated current value ranges from 3.91 µA to 3.99 µ A for bit line resistance ranging from 10 Ω to 1 kΩ. However, the current drops to 2.89 μ? as the resistance rises to 10 kΩ. ?t bit line (BL) resistance of 240 kΩ, the simulated current of the ReRAM array cell is only 689 nA, which is approximately an 82.7% loss compared to the current of BL resistance within the range of 10 Ω–1 kΩ. These results indicate that the effect of BL resistance on the current flow of ReRAM array cells is significant, especially when the resistance increases. Current loss becomes more critical as the array size expands from 2 × 2 to 64 × 64, as illustrated in Figure 9b. For the array size of 2 × 2, the current loss is only 0.43%, while the loss rises to 74.61% as the array size increases to 64 × 64. This aggravation effect is mainly attributed to the larger array having greater resistance in its bit lines, where larger Author Contributions: Investigation, S.K., S.C. and D.K.L.; Supervision, B.-G.P.; Writing – original draft, M.-H.K., voltage drops occur. Through circuit simulation, it is essential to reduce the line resistance in both bit and word lines to accurately measure the array cell current, which is critical to determining the Funding: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Ministry of Science, ICT & Future Planning (2018R1A2A1A05023517) and also supported in part by the Brain Korea 21 Plus Program in 2020. 4.ConflictsConclusofionInterest:s The authors declare no conflict of interest. In this paper, we investigated the switching properties of a Si3N4-based nano-wedge ReRAM device and simulation results for large-sized cross-point arrays. The formation of the wedge structure using TMAH anisotropic wet-etching solution and the effect of variation of the compliance current on the current level were demonstrated. Furthermore, SPICE simulation was carried out to determine the effect of line resistance and array size on the current loss, which is a critical parameter to maximize the accuracy of in-memory computing of neural networks. This research showed that the requirement of a successful neural network depends on minimizing the effect of line resistance, even when the array size increases. Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the accuracyMinistry of Science,neural networksICT & Future[18].Planning (2018R1A2A1A05023517) and also supported in part by the Brain Korea 21 Plus Program in 2020. Publisher Copyright: {\textcopyright} 2020 by the authors. Licensee MDPI, Basel, Switzerland.",
year = "2020",
month = aug,
doi = "10.3390/electronics9081228",
language = "English",
volume = "9",
pages = "1--8",
journal = "Electronics (Switzerland)",
issn = "2079-9292",
publisher = "Multidisciplinary Digital Publishing Institute (MDPI)",
number = "8",
}