A new MOS transistor structural approach (Hot-Carrier-Suppressed MOSFET) capable of substantially suppressing adverse hot-carrier effects while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFET's (Lgate ≤ 0.35 μm) is described. This structure is unique in having a lower doped N− region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFET's have an N− region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions.