MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions: A New Structural Approach

Hyungsoon Shin; T. James Bordelon; Ai F. Tasch; Christine M. Maziar

doi:10.1109/16.144685

MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions: A New Structural Approach

Hyungsoon Shin, T. James Bordelon, Ai F. Tasch, Christine M. Maziar

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

A new MOS transistor structural approach (Hot-Carrier-Suppressed MOSFET) capable of substantially suppressing adverse hot-carrier effects while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFET's (L_gate ≤ 0.35 μm) is described. This structure is unique in having a lower doped N⁻ region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFET's have an N⁻ region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions.

Original language	English
Pages (from-to)	1922-1927
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	39
Issue number	8
DOIs	https://doi.org/10.1109/16.144685
State	Published - Aug 1992

Bibliographical note

Funding Information:
Manuscript received February 15, 1990; revised March 23, 1992. This work was supported in part by the Semiconductor Research Corporation. The review of this paper was arranged by the Editor R. P. Jindal. H. Shin was with the Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78712. He is now with Goldstar Electron Co., Ltd., 16 Woomyeon-Dong, Seocho-Gu, Seoul, Korea. T. J. Bordelon was with the Microelectronics Research Center, The University of Texas at Austin. Austin, TX 78712. He is now with Intel Corp., P.O. Box 58119, Santa Clara, CA 95052-81 19. A. F. Tasch, Jr. and C. M. Maziar are with the Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78712. IEEE Log Number 9201204.

Access to Document

10.1109/16.144685

Cite this

@article{e7e583af318b49ad851b68d7a13a3e65,

title = "MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions: A New Structural Approach",

abstract = "A new MOS transistor structural approach (Hot-Carrier-Suppressed MOSFET) capable of substantially suppressing adverse hot-carrier effects while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFET's (Lgate ≤ 0.35 μm) is described. This structure is unique in having a lower doped N− region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFET's have an N− region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions.",

author = "Hyungsoon Shin and Bordelon, {T. James} and Tasch, {Ai F.} and Maziar, {Christine M.}",

note = "Funding Information: Manuscript received February 15, 1990; revised March 23, 1992. This work was supported in part by the Semiconductor Research Corporation. The review of this paper was arranged by the Editor R. P. Jindal. H. Shin was with the Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78712. He is now with Goldstar Electron Co., Ltd., 16 Woomyeon-Dong, Seocho-Gu, Seoul, Korea. T. J. Bordelon was with the Microelectronics Research Center, The University of Texas at Austin. Austin, TX 78712. He is now with Intel Corp., P.O. Box 58119, Santa Clara, CA 95052-81 19. A. F. Tasch, Jr. and C. M. Maziar are with the Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78712. IEEE Log Number 9201204.",

year = "1992",

month = aug,

doi = "10.1109/16.144685",

language = "English",

volume = "39",

pages = "1922--1927",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "8",

}

TY - JOUR

T1 - MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions

T2 - A New Structural Approach

AU - Shin, Hyungsoon

AU - Bordelon, T. James

AU - Tasch, Ai F.

AU - Maziar, Christine M.

N1 - Funding Information: Manuscript received February 15, 1990; revised March 23, 1992. This work was supported in part by the Semiconductor Research Corporation. The review of this paper was arranged by the Editor R. P. Jindal. H. Shin was with the Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78712. He is now with Goldstar Electron Co., Ltd., 16 Woomyeon-Dong, Seocho-Gu, Seoul, Korea. T. J. Bordelon was with the Microelectronics Research Center, The University of Texas at Austin. Austin, TX 78712. He is now with Intel Corp., P.O. Box 58119, Santa Clara, CA 95052-81 19. A. F. Tasch, Jr. and C. M. Maziar are with the Microelectronics Research Center, The University of Texas at Austin, Austin, TX 78712. IEEE Log Number 9201204.

PY - 1992/8

Y1 - 1992/8

N2 - A new MOS transistor structural approach (Hot-Carrier-Suppressed MOSFET) capable of substantially suppressing adverse hot-carrier effects while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFET's (Lgate ≤ 0.35 μm) is described. This structure is unique in having a lower doped N− region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFET's have an N− region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions.

AB - A new MOS transistor structural approach (Hot-Carrier-Suppressed MOSFET) capable of substantially suppressing adverse hot-carrier effects while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFET's (Lgate ≤ 0.35 μm) is described. This structure is unique in having a lower doped N− region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFET's have an N− region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions.

UR - http://www.scopus.com/inward/record.url?scp=0026910749&partnerID=8YFLogxK

U2 - 10.1109/16.144685

DO - 10.1109/16.144685

M3 - Article

AN - SCOPUS:0026910749

SN - 0018-9383

VL - 39

SP - 1922

EP - 1927

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 8

ER -

MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions: A New Structural Approach

Abstract

Bibliographical note

Access to Document

Fingerprint

Cite this