More physical understanding of current characteristics of tunneling field-effect transistor leveraged by gate positions and properties through dual-gate and gate-all-around structuring

In this work, a tunneling field-effect transistor (TFET) in the structure that can maximize the electrostatic effects in determining its electrical performances is optimally designed and characterized. The featured device structure includes gate-all-around (GAA) channel and dual gates (DuGs) identified as control gate (CG) and adjust gate (AG), respectively. Not along with the design tasks, more fundamental studies on the effects of respective gates on device performances are sought. It has been found that the relatively different vicinities of the DuGs to source and drain junctions have differentiable dominances in controlling the primary direct-current (DC) parameters of the TFET including threshold voltage (V_th), on-state current (I_on), subthreshold swing (S), and on/off current ratio (I_on/I_off). For the systematic study, four different cases have been presumably schemed giving the degree of freedom in gate workfunctions and inter-gate connectivity. It has been found that the CG at the source side more effectively modulates V_th, I_off, and S, while the AG at the drain side shows the higher controllability over I_on and I_on/I_off of the TFET. An optimally designed GAA DuG demonstrated I_on/I_off > 10¹¹ along with a small S of 14.6 mV/dec, which supports the strong potential of the GAA DuG TFET in the low-power applications.