Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems

Yunjoo Park; Hyokyung Bahn

doi:10.1109/ICISCE50968.2020.00178

Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems

Yunjoo Park, Hyokyung Bahn

Department of Computer Science & Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Non-volatile memory (NVM) is recently attracting interest as a new storage device, and the traditional memory management system designed for hard disk drive (HDD) needs to be reconsidered. In this paper, we revisit the memory management system that adopts NVM as a storage device. In particular, we quantify the memory access latency as the TLB miss rate and the page fault rate are varied. By doing so, we observe that the memory access latency is sensitive to the page size when NVM storage is adopted. We find the reason from the TLB miss rate, which has the increased influence on the memory access latency in comparison with the page fault rate, and there is a trade-off relation between the TLB miss rate and the page fault rate as the page size is varied. To handle such situations, we present a memory access latency model that reflects the page fault rate and the TLB miss rate accurately as a function of the page size. Specifically, we show that the power fit and the exponential fit with two terms are appropriate for the fitting of the TLB miss rate and the page fault rate curves, respectively.

Original language	English
Title of host publication	Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020
Editors	Shaozi Li, Ying Dai, Jianwei Ma, Yun Cheng
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	856-860
Number of pages	5
ISBN (Electronic)	9781728164069
DOIs	https://doi.org/10.1109/ICISCE50968.2020.00178
State	Published - Dec 2020
Event	7th International Conference on Information Science and Control Engineering, ICISCE 2020 - Changsha, Hunan, China Duration: 18 Dec 2020 → 20 Dec 2020

Publication series

Name	Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020

Conference

Conference	7th International Conference on Information Science and Control Engineering, ICISCE 2020
Country/Territory	China
City	Changsha, Hunan
Period	18/12/20 → 20/12/20

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by the ICT R&D program of MSIP/IITP (2019-0-00074, developing system software technologies for emerging new memory that adaptively learn workload characteristics) and also by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2019R1A2C1009275).

Publisher Copyright:
© 2020 IEEE.

Keywords

NVM
non-volatile memory
page fault
storage

Access to Document

10.1109/ICISCE50968.2020.00178

Cite this

Park, Y., & Bahn, H. (2020). Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems. In S. Li, Y. Dai, J. Ma, & Y. Cheng (Eds.), Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020 (pp. 856-860). (Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICISCE50968.2020.00178

Park, Yunjoo ; Bahn, Hyokyung. / Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems. Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020. editor / Shaozi Li ; Ying Dai ; Jianwei Ma ; Yun Cheng. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 856-860 (Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020).

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abstract = "Non-volatile memory (NVM) is recently attracting interest as a new storage device, and the traditional memory management system designed for hard disk drive (HDD) needs to be reconsidered. In this paper, we revisit the memory management system that adopts NVM as a storage device. In particular, we quantify the memory access latency as the TLB miss rate and the page fault rate are varied. By doing so, we observe that the memory access latency is sensitive to the page size when NVM storage is adopted. We find the reason from the TLB miss rate, which has the increased influence on the memory access latency in comparison with the page fault rate, and there is a trade-off relation between the TLB miss rate and the page fault rate as the page size is varied. To handle such situations, we present a memory access latency model that reflects the page fault rate and the TLB miss rate accurately as a function of the page size. Specifically, we show that the power fit and the exponential fit with two terms are appropriate for the fitting of the TLB miss rate and the page fault rate curves, respectively.",

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note = "Funding Information: ACKNOWLEDGMENT This work was supported by the ICT R&D program of MSIP/IITP (2019-0-00074, developing system software technologies for emerging new memory that adaptively learn workload characteristics) and also by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2019R1A2C1009275). Publisher Copyright: {\textcopyright} 2020 IEEE.; 7th International Conference on Information Science and Control Engineering, ICISCE 2020 ; Conference date: 18-12-2020 Through 20-12-2020",

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Park, Y & Bahn, H 2020, Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems. in S Li, Y Dai, J Ma & Y Cheng (eds), Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020. Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020, Institute of Electrical and Electronics Engineers Inc., pp. 856-860, 7th International Conference on Information Science and Control Engineering, ICISCE 2020, Changsha, Hunan, China, 18/12/20. https://doi.org/10.1109/ICISCE50968.2020.00178

Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems. / Park, Yunjoo; Bahn, Hyokyung.
Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020. ed. / Shaozi Li; Ying Dai; Jianwei Ma; Yun Cheng. Institute of Electrical and Electronics Engineers Inc., 2020. p. 856-860 (Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Non-volatile memory (NVM) is recently attracting interest as a new storage device, and the traditional memory management system designed for hard disk drive (HDD) needs to be reconsidered. In this paper, we revisit the memory management system that adopts NVM as a storage device. In particular, we quantify the memory access latency as the TLB miss rate and the page fault rate are varied. By doing so, we observe that the memory access latency is sensitive to the page size when NVM storage is adopted. We find the reason from the TLB miss rate, which has the increased influence on the memory access latency in comparison with the page fault rate, and there is a trade-off relation between the TLB miss rate and the page fault rate as the page size is varied. To handle such situations, we present a memory access latency model that reflects the page fault rate and the TLB miss rate accurately as a function of the page size. Specifically, we show that the power fit and the exponential fit with two terms are appropriate for the fitting of the TLB miss rate and the page fault rate curves, respectively.

AB - Non-volatile memory (NVM) is recently attracting interest as a new storage device, and the traditional memory management system designed for hard disk drive (HDD) needs to be reconsidered. In this paper, we revisit the memory management system that adopts NVM as a storage device. In particular, we quantify the memory access latency as the TLB miss rate and the page fault rate are varied. By doing so, we observe that the memory access latency is sensitive to the page size when NVM storage is adopted. We find the reason from the TLB miss rate, which has the increased influence on the memory access latency in comparison with the page fault rate, and there is a trade-off relation between the TLB miss rate and the page fault rate as the page size is varied. To handle such situations, we present a memory access latency model that reflects the page fault rate and the TLB miss rate accurately as a function of the page size. Specifically, we show that the power fit and the exponential fit with two terms are appropriate for the fitting of the TLB miss rate and the page fault rate curves, respectively.

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Park Y, Bahn H. Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems. In Li S, Dai Y, Ma J, Cheng Y, editors, Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 856-860. (Proceedings - 2020 7th International Conference on Information Science and Control Engineering, ICISCE 2020). doi: 10.1109/ICISCE50968.2020.00178

Modeling of the TLB miss rate and the Page fault rate for NVM-based Storage Systems

Abstract

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Keywords

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