Minimization of gate-induced drain leakage by controlling gate underlap length for low-standby-power operation of 20-nm-level four-terminal silicon-on-insulator fin-shaped field effect transistor

Engineering

• Field-Effect Transistor 100%
• Silicon on Insulator 100%
• Gate Induced Drain Leakage 100%
• Drain Junction 33%
• Field Effect Transistor 33%
• Element Group 33%
• Process Condition 16%
• Metal-Oxide-Semiconductor Field-Effect Transistor 16%
• Carrier Lifetime 16%
• Minority Carriers 16%
• Device Scaling 16%