TY - GEN
T1 - Low-power hybrid turbo decoding based on reverse calculation
AU - Choi, Hye Mi
AU - Kim, Ji Hoon
AU - Park, In Cheol
PY - 2006
Y1 - 2006
N2 - As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the Max-log-MAP algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-MAP, that results in a similar BER performance to the log-MAP algorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-MAP turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.
AB - As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the Max-log-MAP algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-MAP, that results in a similar BER performance to the log-MAP algorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-MAP turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.
UR - http://www.scopus.com/inward/record.url?scp=34547270453&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:34547270453
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2053
EP - 2056
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -