Low-crosstalk 10-Gb/s flip-chip array module for parallel optical interconnects

Sang Hyun Park, Sung Min Park, Hyo Hoon Park, Chul Soon Park

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

A 10-Gb/s optical receiver array with low interchannel crosstalk is realized by exploiting an InGaP-GaAs heterojunction bipolar transistor technology in a three-dimensional multilayer low-temperature cofiring ceramics (LTCC) module. Neutralization feedback circuit with LTCC embedded bus structure is proposed to suppress significant high-frequency crosstalk from on-chip bus and intermetallic capacitance. This module demonstrates 5 dB better suppressed-coupling than a conventional on-chip bus module with 0.8-dB power penalty.

Original languageEnglish
Pages (from-to)1516-1518
Number of pages3
JournalIEEE Photonics Technology Letters
Volume17
Issue number7
DOIs
StatePublished - Jul 2005

Bibliographical note

Funding Information:
Manuscript received January 27, 2005; revised March 9, 2005. This work was supported in part by the Ministry of Science and Technology of Korea and by the Korea Institute of Science and Technology Evaluation and Planning (KISTEP). S. H. Park, H.-H. Park, and C. S. Park are with the School of Engineering, Information and Communications University, Daejeon 305-714, Korea (e-mail: totoro@icu.ac.kr). S. M. Park is with the Department of Information Electronics Engineering, Ewha Womans University, Seoul 120-750, Korea (e-mail: smpark@ewha.ac.kr). Digital Object Identifier 10.1109/LPT.2005.848562 Fig. 1. (a) Block diagram of a single channel receiver, where C is the off-chip balancing capacitor and (b) schematic diagram of the NG stage using C of Q asC .

Keywords

  • Channel crosstalk
  • Flip-chip
  • Low-temperature cofiring ceramic (LTCC) substrate
  • Parallel optical interconnects
  • Transimpedance amplifier

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