We proposed a high-performance elliptic curve cryptography (ECC) processor over NIST prime fields. Instead of applying a full modular reduction to a 2k-bit product, the proposed partial modular reduction method iteratively performs reductions on partial products whose bit length is slightly greater than k, where k is the bit length of field elements. As a result, the computational complexity of modular multiplication (MM) was significantly reduced. Moreover, the amount of computation is configurable by parameterizing the size of the partial products. This is a very desirable characteristic of the proposed ECC processor, because the hardware complexity and processing time of the entire ECC processor can be adjusted according to the requirements of various Internet of Things environments. Including the proposed MM module, finite field operation modules are integrated into a single module to further reduce the required resources. The proposed ECC processor synthesized using 180-nm CMOS process technology can perform a 256-bit elliptic curve point multiplication in 0.20-0.74 ms with 144.8k-65.4k gate counts. These results and the experimental results in various FPGA devices show that the proposed ECC processor has significantly better throughput per area than the previously reported ones.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|State||Published - Nov 2018|
- Elliptic curve cryptography (ECC)
- finite field
- hardware implementation
- partial modular reduction