Limitations of LDD Types of Structures in Deep-Submicrometer MOS Technology

Al F. Tasch; H. Shin; T. J. Bordelon; Christine M. Maziar

doi:10.1109/55.63018

Limitations of LDD Types of Structures in Deep-Submicrometer MOS Technology

Al F. Tasch, H. Shin, T. J. Bordelon, Christine M. Maziar

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

Lightly doped drain (LDD) types of MOSFET structures have been analyzed in detail in order to understand the issues and trade-offs in the application of these structures to deep-submicrometer technology (Lgate ≤ 0.35 μm) in which the minimum feature size of the technology is exploited as the total gate length of the device. Because of considerable channel doping compensation resulting from the desired graded drain profile of the N− region, larger and unacceptable charge-sharing effects are encountered. The problem can be avoided if the LDD N− region is shallow and steeply profiled. However, this leads to unacceptably high hot-carrier generation rates. This major conflict in design requirements (suppression of charge sharing as well as reduction of hot-carrier effects) results in serious limitations of LDD MOSFET’s in their applicability to deep-submicrometer technology.

Original language	English
Pages (from-to)	517-519
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	11
Issue number	11
DOIs	https://doi.org/10.1109/55.63018
State	Published - Nov 1990

Bibliographical note

Funding Information:
Manuscript received March 6, 1990; revised August 12, 1990. This work was supported in part by the Semiconductor Research Corporation and the Texas Advanced Technology Program. The authors are with the Microelectronics Research Center, University of Texas, Austin, TX 78712. IEEE Log Number 9040234.

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title = "Limitations of LDD Types of Structures in Deep-Submicrometer MOS Technology",

abstract = "Lightly doped drain (LDD) types of MOSFET structures have been analyzed in detail in order to understand the issues and trade-offs in the application of these structures to deep-submicrometer technology (Lgate ≤ 0.35 μm) in which the minimum feature size of the technology is exploited as the total gate length of the device. Because of considerable channel doping compensation resulting from the desired graded drain profile of the N− region, larger and unacceptable charge-sharing effects are encountered. The problem can be avoided if the LDD N− region is shallow and steeply profiled. However, this leads to unacceptably high hot-carrier generation rates. This major conflict in design requirements (suppression of charge sharing as well as reduction of hot-carrier effects) results in serious limitations of LDD MOSFET{\textquoteright}s in their applicability to deep-submicrometer technology.",

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note = "Funding Information: Manuscript received March 6, 1990; revised August 12, 1990. This work was supported in part by the Semiconductor Research Corporation and the Texas Advanced Technology Program. The authors are with the Microelectronics Research Center, University of Texas, Austin, TX 78712. IEEE Log Number 9040234.",

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AU - Maziar, Christine M.

N1 - Funding Information: Manuscript received March 6, 1990; revised August 12, 1990. This work was supported in part by the Semiconductor Research Corporation and the Texas Advanced Technology Program. The authors are with the Microelectronics Research Center, University of Texas, Austin, TX 78712. IEEE Log Number 9040234.

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N2 - Lightly doped drain (LDD) types of MOSFET structures have been analyzed in detail in order to understand the issues and trade-offs in the application of these structures to deep-submicrometer technology (Lgate ≤ 0.35 μm) in which the minimum feature size of the technology is exploited as the total gate length of the device. Because of considerable channel doping compensation resulting from the desired graded drain profile of the N− region, larger and unacceptable charge-sharing effects are encountered. The problem can be avoided if the LDD N− region is shallow and steeply profiled. However, this leads to unacceptably high hot-carrier generation rates. This major conflict in design requirements (suppression of charge sharing as well as reduction of hot-carrier effects) results in serious limitations of LDD MOSFET’s in their applicability to deep-submicrometer technology.

AB - Lightly doped drain (LDD) types of MOSFET structures have been analyzed in detail in order to understand the issues and trade-offs in the application of these structures to deep-submicrometer technology (Lgate ≤ 0.35 μm) in which the minimum feature size of the technology is exploited as the total gate length of the device. Because of considerable channel doping compensation resulting from the desired graded drain profile of the N− region, larger and unacceptable charge-sharing effects are encountered. The problem can be avoided if the LDD N− region is shallow and steeply profiled. However, this leads to unacceptably high hot-carrier generation rates. This major conflict in design requirements (suppression of charge sharing as well as reduction of hot-carrier effects) results in serious limitations of LDD MOSFET’s in their applicability to deep-submicrometer technology.

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Limitations of LDD Types of Structures in Deep-Submicrometer MOS Technology

Abstract

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