Abstract
A new last-level cache replacement policy for systems with a phasechange memory (PCM) main memory is presented. The proposed policy aims at reducing the write traffic to PCM by considering the fine-grained dirtiness of cache blocks when making a replacement decision. Experimental results show that the proposed policy reduces the write traffic to the PCM by 26 and 17% on average and up to 52 and 33% compared to not recently used and re-reference interval prediction, respectively
| Original language | English |
|---|---|
| Pages (from-to) | 1607-1609 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 49 |
| Issue number | 25 |
| DOIs | |
| State | Published - 5 Dec 2013 |