Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

J. G. Yun; Y. Kim; I. H. Park; S. J. Cho; J. H. Lee; D. H. Kim; G. S. Lee; J. Y. Song; J. D. Lee; B. G. Park

doi:10.1109/NMDC.2006.4388845

Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

J. G. Yun, Y. Kim, I. H. Park, S. J. Cho, J. H. Lee, D. H. Kim, G. S. Lee, J. Y. Song, J. D. Lee, B. G. Park

Electronic and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Investigation of 4-bit SONOS nonvolatile memory with 3-dimentional structure has been done using a 3-dimensional numerical simulation tool. The impact of channel length and the interference of stored charge on the opposite side of channel are observed by changing the channel length and Sifin width. It is estimated that the device can be scaled down to gate length/fin width of 70/30 nm with sufficient V_TH window margin of 2 V.

Original language	English
Title of host publication	2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Pages	214-215
Number of pages	2
DOIs	https://doi.org/10.1109/NMDC.2006.4388845
State	Published - 2006
Event	2006 IEEE Nanotechnology Materials and Devices Conference, NMDC - Gyeongju, Korea, Republic of Duration: 22 Oct 2006 → 25 Oct 2006

Publication series

Name	2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Volume	1

Conference

Conference	2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Country/Territory	Korea, Republic of
City	Gyeongju
Period	22/10/06 → 25/10/06

Keywords

3-dimensional numerical simulation
3-dimensional structure
4-bit SONOS device
V window

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10.1109/NMDC.2006.4388845

Cite this

Yun, J. G., Kim, Y., Park, I. H., Cho, S. J., Lee, J. H., Kim, D. H., Lee, G. S., Song, J. Y., Lee, J. D., & Park, B. G. (2006). Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation. In 2006 IEEE Nanotechnology Materials and Devices Conference, NMDC (pp. 214-215). Article 4388845 (2006 IEEE Nanotechnology Materials and Devices Conference, NMDC; Vol. 1). https://doi.org/10.1109/NMDC.2006.4388845

@inproceedings{1a6fdf112ecd4633b02fadcb77dea21c,

title = "Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation",

abstract = "Investigation of 4-bit SONOS nonvolatile memory with 3-dimentional structure has been done using a 3-dimensional numerical simulation tool. The impact of channel length and the interference of stored charge on the opposite side of channel are observed by changing the channel length and Sifin width. It is estimated that the device can be scaled down to gate length/fin width of 70/30 nm with sufficient VTH window margin of 2 V.",

keywords = "3-dimensional numerical simulation, 3-dimensional structure, 4-bit SONOS device, V window",

author = "Yun, {J. G.} and Y. Kim and Park, {I. H.} and Cho, {S. J.} and Lee, {J. H.} and Kim, {D. H.} and Lee, {G. S.} and Song, {J. Y.} and Lee, {J. D.} and Park, {B. G.}",

year = "2006",

doi = "10.1109/NMDC.2006.4388845",

language = "English",

isbn = "1424405408",

series = "2006 IEEE Nanotechnology Materials and Devices Conference, NMDC",

pages = "214--215",

booktitle = "2006 IEEE Nanotechnology Materials and Devices Conference, NMDC",

note = "2006 IEEE Nanotechnology Materials and Devices Conference, NMDC ; Conference date: 22-10-2006 Through 25-10-2006",

}

Yun, JG, Kim, Y, Park, IH, Cho, SJ, Lee, JH, Kim, DH, Lee, GS, Song, JY, Lee, JD & Park, BG 2006, Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation. in 2006 IEEE Nanotechnology Materials and Devices Conference, NMDC., 4388845, 2006 IEEE Nanotechnology Materials and Devices Conference, NMDC, vol. 1, pp. 214-215, 2006 IEEE Nanotechnology Materials and Devices Conference, NMDC, Gyeongju, Korea, Republic of, 22/10/06. https://doi.org/10.1109/NMDC.2006.4388845

Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation. / Yun, J. G.; Kim, Y.; Park, I. H. et al.
2006 IEEE Nanotechnology Materials and Devices Conference, NMDC. 2006. p. 214-215 4388845 (2006 IEEE Nanotechnology Materials and Devices Conference, NMDC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

AU - Yun, J. G.

AU - Kim, Y.

AU - Park, I. H.

AU - Cho, S. J.

AU - Lee, J. H.

AU - Kim, D. H.

AU - Lee, G. S.

AU - Song, J. Y.

AU - Lee, J. D.

AU - Park, B. G.

PY - 2006

Y1 - 2006

N2 - Investigation of 4-bit SONOS nonvolatile memory with 3-dimentional structure has been done using a 3-dimensional numerical simulation tool. The impact of channel length and the interference of stored charge on the opposite side of channel are observed by changing the channel length and Sifin width. It is estimated that the device can be scaled down to gate length/fin width of 70/30 nm with sufficient VTH window margin of 2 V.

AB - Investigation of 4-bit SONOS nonvolatile memory with 3-dimentional structure has been done using a 3-dimensional numerical simulation tool. The impact of channel length and the interference of stored charge on the opposite side of channel are observed by changing the channel length and Sifin width. It is estimated that the device can be scaled down to gate length/fin width of 70/30 nm with sufficient VTH window margin of 2 V.

KW - 3-dimensional numerical simulation

KW - 3-dimensional structure

KW - 4-bit SONOS device

KW - V window

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U2 - 10.1109/NMDC.2006.4388845

DO - 10.1109/NMDC.2006.4388845

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BT - 2006 IEEE Nanotechnology Materials and Devices Conference, NMDC

T2 - 2006 IEEE Nanotechnology Materials and Devices Conference, NMDC

Y2 - 22 October 2006 through 25 October 2006

ER -

Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

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Keywords

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