Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

J. G. Yun, Y. Kim, I. H. Park, S. J. Cho, J. H. Lee, D. H. Kim, G. S. Lee, J. Y. Song, J. D. Lee, B. G. Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Investigation of 4-bit SONOS nonvolatile memory with 3-dimentional structure has been done using a 3-dimensional numerical simulation tool. The impact of channel length and the interference of stored charge on the opposite side of channel are observed by changing the channel length and Sifin width. It is estimated that the device can be scaled down to gate length/fin width of 70/30 nm with sufficient VTH window margin of 2 V.

Original languageEnglish
Title of host publication2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Pages214-215
Number of pages2
DOIs
StatePublished - 2006
Event2006 IEEE Nanotechnology Materials and Devices Conference, NMDC - Gyeongju, Korea, Republic of
Duration: 22 Oct 200625 Oct 2006

Publication series

Name2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Volume1

Conference

Conference2006 IEEE Nanotechnology Materials and Devices Conference, NMDC
Country/TerritoryKorea, Republic of
CityGyeongju
Period22/10/0625/10/06

Keywords

  • 3-dimensional numerical simulation
  • 3-dimensional structure
  • 4-bit SONOS device
  • V window

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