Abstract
In this paper, we propose a double-gate one-transistor dynamic random-access memory (1T DRAM) with middle partial insulation (MPI) structure for low power application. Low power operation with the gate-induced drain leakage (GIDL) programming method can be obtained while maintaining the original advantages of MPI 1TDRAM. The optimization of the MPI 1T-DRAM device for the GIDL method is investigated with technology computer-aided design (TCAD). High current ratio and low power consumption are obtained from the proposed 1T-DRAM device. Optimal device design in terms of barrier insulator length and fin width have been carried out for improvements of device performances and reliability.
Original language | English |
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Pages (from-to) | 165-171 |
Number of pages | 7 |
Journal | Journal of Semiconductor Technology and Science |
Volume | 19 |
Issue number | 2 |
DOIs | |
State | Published - Apr 2019 |
Bibliographical note
Publisher Copyright:© 2019, Institute of Electronics Engineers of Korea. All rights reserved.
Keywords
- 1T DRAM
- Gate-induced drain leakage (GIDL)
- Middle partial insulation
- TCAD