Investigation and optimization of double-gate MPI 1T DRAM with gate-induced drain leakage operation

Jongmin Ha, Jae Yoon Lee, Myeongseon Kim, Seongjae Cho, Il Hwan Cho

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

In this paper, we propose a double-gate one-transistor dynamic random-access memory (1T DRAM) with middle partial insulation (MPI) structure for low power application. Low power operation with the gate-induced drain leakage (GIDL) programming method can be obtained while maintaining the original advantages of MPI 1TDRAM. The optimization of the MPI 1T-DRAM device for the GIDL method is investigated with technology computer-aided design (TCAD). High current ratio and low power consumption are obtained from the proposed 1T-DRAM device. Optimal device design in terms of barrier insulator length and fin width have been carried out for improvements of device performances and reliability.

Original languageEnglish
Pages (from-to)165-171
Number of pages7
JournalJournal of Semiconductor Technology and Science
Volume19
Issue number2
DOIs
StatePublished - Apr 2019

Bibliographical note

Publisher Copyright:
© 2019, Institute of Electronics Engineers of Korea. All rights reserved.

Keywords

  • 1T DRAM
  • Gate-induced drain leakage (GIDL)
  • Middle partial insulation
  • TCAD

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