Highly scalable 3-D NAND-NOR hybrid-type dual bit per cell flash memory devices with an additional cut-off gate

In this work, a nonvolatile memory (NVM) device of novel structure in 3 dimensions is introduced, and its operation physics is validated. It is based on a pillar structure in which two identical storage nodes are located for dual-bit operation. The two storage nodes on neighboring pillars are controlled by using one common control gate so that the space between silicon pillars can be further reduced. For compatibility with conventional memory operations, an additional cut-off gate is constructed under the common control gate. This is considered as the ultimate form for a 3-D nonvolatile memory device based on a double-gate structure. The underlying physics is explained, and the operational schemes are validated in various aspects by using a numerical device simulation. Also, critical issues in device design for higher reliability are discussed.