Highly compact and accurate circuit-level macro modeling of gate-All-Around charge-Trap flash memory

In this paper, a highly reliable circuit model of gate-All-Around (GAA) charge-Trap flash (CTF) memory cell is proposed, considering the transient behaviors for describing the program operations with improved accuracy. Although several compact models have been reported in the previous literature, time-dependent behaviors have not been precisely reflected and the failures tend to get worse as the operation time elapses. Furthermore, the developed SPICE models in this work have been verified by the measurement results of the fabricated flash memory cells having silicon-oxide-nitride-oxide-silicon (SONOS). This more realistic model would be beneficial in designing the system architectures and setting up the operation schemes for the leading three-dimensional (3D) stack CTF memory.