High throughput radix-4 SISO decoding architecture with reduced memory requirement

Wooseok Byun, Hyeji Kim, Ji Hoon Kim

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)- based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

Original languageEnglish
Pages (from-to)407-418
Number of pages12
JournalJournal of Semiconductor Technology and Science
Volume14
Issue number4
DOIs
StatePublished - 2014

Keywords

  • Add-compare-select
  • High-throughput
  • Retiming technique
  • Signal processing
  • SISO decoder

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