High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling

Injun Choi, Ji Hoon Kim

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


Non-binary LDPC (NB-LDPC) codes offer better error correcting performance than their binary counterparts. However, to achieve excellent performance, decoding complexity and large memory are required, which makes it difficult to implement the high-throughput decoder. This paper presents a fully overlapped NB-LDPC decoder using three proposed techniques to improve throughput performance. First, an early bubble check is presented to reduce the initialization latency of the check node processing (CNP). Second, the CNP and variable node processing (VNP) are overlapped with the proposed backward memory scan method to hide the CNP latency within the VNP. Finally, we propose a redundant memory reuse technique to further decrease the latency of a single decoding iteration. We implemented the high-throughput decoder for (160, 80) regular (2, 4) NB-LDPC code over GF (64). The iteration latency was decreased by up to 57.5% with our three proposed methods. The proposed decoder achieved a throughput of 2.22 Gb/s at a 625-MHz frequency with 2.96-M gates in a 65-nm CMOS process. The proposed decoder showed outstanding area efficiency compared with the state-of-the-art decoders.

Original languageEnglish
Article number7880589
Pages (from-to)1937-1948
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number7
StatePublished - Jul 2017

Bibliographical note

Funding Information:
This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Science

Publisher Copyright:
© 2017 IEEE.


  • NB-LDPC codes
  • low latency check node processing
  • memory reuse technique
  • overlap schedule


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