TY - JOUR
T1 - High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling
AU - Choi, Injun
AU - Kim, Ji Hoon
N1 - Funding Information:
This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Science
Publisher Copyright:
© 2017 IEEE.
PY - 2017/7
Y1 - 2017/7
N2 - Non-binary LDPC (NB-LDPC) codes offer better error correcting performance than their binary counterparts. However, to achieve excellent performance, decoding complexity and large memory are required, which makes it difficult to implement the high-throughput decoder. This paper presents a fully overlapped NB-LDPC decoder using three proposed techniques to improve throughput performance. First, an early bubble check is presented to reduce the initialization latency of the check node processing (CNP). Second, the CNP and variable node processing (VNP) are overlapped with the proposed backward memory scan method to hide the CNP latency within the VNP. Finally, we propose a redundant memory reuse technique to further decrease the latency of a single decoding iteration. We implemented the high-throughput decoder for (160, 80) regular (2, 4) NB-LDPC code over GF (64). The iteration latency was decreased by up to 57.5% with our three proposed methods. The proposed decoder achieved a throughput of 2.22 Gb/s at a 625-MHz frequency with 2.96-M gates in a 65-nm CMOS process. The proposed decoder showed outstanding area efficiency compared with the state-of-the-art decoders.
AB - Non-binary LDPC (NB-LDPC) codes offer better error correcting performance than their binary counterparts. However, to achieve excellent performance, decoding complexity and large memory are required, which makes it difficult to implement the high-throughput decoder. This paper presents a fully overlapped NB-LDPC decoder using three proposed techniques to improve throughput performance. First, an early bubble check is presented to reduce the initialization latency of the check node processing (CNP). Second, the CNP and variable node processing (VNP) are overlapped with the proposed backward memory scan method to hide the CNP latency within the VNP. Finally, we propose a redundant memory reuse technique to further decrease the latency of a single decoding iteration. We implemented the high-throughput decoder for (160, 80) regular (2, 4) NB-LDPC code over GF (64). The iteration latency was decreased by up to 57.5% with our three proposed methods. The proposed decoder achieved a throughput of 2.22 Gb/s at a 625-MHz frequency with 2.96-M gates in a 65-nm CMOS process. The proposed decoder showed outstanding area efficiency compared with the state-of-the-art decoders.
KW - NB-LDPC codes
KW - low latency check node processing
KW - memory reuse technique
KW - overlap schedule
UR - http://www.scopus.com/inward/record.url?scp=85015936292&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2017.2677518
DO - 10.1109/TCSI.2017.2677518
M3 - Article
AN - SCOPUS:85015936292
SN - 1549-8328
VL - 64
SP - 1937
EP - 1948
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 7
M1 - 7880589
ER -