High-speed low-power junctionless field-effect transistor with ultra-thin poly-si channel for sub-10-nm technology node

Youngmin Kim, Junsoo Lee, Yongbeom Cho, Won Jae Lee, Seongjae Cho

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

Original languageEnglish
Pages (from-to)159-165
Number of pages7
JournalJournal of Semiconductor Technology and Science
Volume16
Issue number2
DOIs
StatePublished - Apr 2016

Bibliographical note

Publisher Copyright:
© 2016, Institute of Electronics Engineers of Korea. All rights reserved.

Keywords

  • Device simulation
  • High-speed operation
  • Junctionless field-effect transistor
  • Low power consumption
  • Low thermal budget
  • Si CMOS
  • Ultra-thin poly-si channel

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