High-Level AMBA Monitoring Platform for SoC Architecture Exploration

Jaeyun Lim, Yujin Jeon, Eunkyung Ham, Ji Hoon Kim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As a System on Chip (SoC) hardware complexity grows dramatically, it becomes more difficult to find the optimal SoC architecture with various hardware IPs. Accordingly, SoC architecture exploration should be performed before the chip-level implementation where various types of on-chip interconnect topology are compared according to the on-chip traffic patterns from a number of hardware IPs in terms of area, transaction latency, power consumption, etc. In this paper, we propose a high-level AMBA (Advanced Microcontroller Bus Architecture) Monitoring Platform where various traffic statistics can be obtained with C++ modeling using open-source Verilator. For the evaluation, we built the baseline SoC platform with Arm Cortex-M4F CPU core and various hardware IPs. With the proposed high-level AMBA monitoring platform, the high-level C++ modeling of on-chip traffic analysis allows to find optimal AMBA on-chip interconnects in the early stages with fast analysis time based on the on-chip traffic analysis.

Original languageEnglish
Title of host publication2023 International Conference on Electronics, Information, and Communication, ICEIC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350320213
DOIs
StatePublished - 2023
Event2023 International Conference on Electronics, Information, and Communication, ICEIC 2023 - Singapore, Singapore
Duration: 5 Feb 20238 Feb 2023

Publication series

Name2023 International Conference on Electronics, Information, and Communication, ICEIC 2023

Conference

Conference2023 International Conference on Electronics, Information, and Communication, ICEIC 2023
Country/TerritorySingapore
CitySingapore
Period5/02/238/02/23

Bibliographical note

Funding Information:
ACKNOWLEDGMENT The EDA tool was supported by the IC Design Education Center (IDEC), Korea. This work was supported by the Industrial Fundamental Technology Development Program (No. 20019367, Development of Low Power AI Architecture for AIoT) funded by the Ministry of Trade, Industry & Energy (MOTIE) of Korea.

Publisher Copyright:
© 2023 IEEE.

Keywords

  • AMBA
  • Hardware design
  • On-chip interconnect
  • SoC Platform
  • Verilator

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