Abstract
This paper presents a large-scale digital neuromorphic processor for spiking neural network emulation. The processor is fabricated in a 28 nm CMOS and occupies a 9.00 mm2 die area for 262,144 neurons. A time-embedded floating-point leaky integrate-and-fire neuron model is implemented to reduce the size of SRAM and the number of SRAM accesses. It achieves a high-density neuron integration (34.9 k neurons/mm2), which is 13 times higher than other state-of-the-art designs. Additionally, it achieves a high-dynamic range synapse (8-bit floating-point) and low energy consumption (28.26 pJ/synaptic operation).
| Original language | English |
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| Title of host publication | 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 322-326 |
| Number of pages | 5 |
| ISBN (Electronic) | 9798350383638 |
| DOIs | |
| State | Published - 2024 |
| Event | 6th IEEE International Conference on AI Circuits and Systems, AICAS 2024 - Abu Dhabi, United Arab Emirates Duration: 22 Apr 2024 → 25 Apr 2024 |
Publication series
| Name | 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings |
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Conference
| Conference | 6th IEEE International Conference on AI Circuits and Systems, AICAS 2024 |
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| Country/Territory | United Arab Emirates |
| City | Abu Dhabi |
| Period | 22/04/24 → 25/04/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- Customized floating-point number
- energy-efficient
- high-precision synapse
- large-scale system
- spiking neural network
