High cell-efficiency synchronous MRAM adopting unified bit-line cache

D. J. Kim; J. H. Ko; C. H. Cho; Y. I. Park; D. W. Kang; K. S. Min; D. M. Kim; S. J. Lee; H. S. Shin

doi:10.1049/el:20030783

High cell-efficiency synchronous MRAM adopting unified bit-line cache

D. J. Kim, J. H. Ko, C. H. Cho, Y. I. Park, D. W. Kang, K. S. Min, D. M. Kim, S. J. Lee, H. S. Shin

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.

Original language	English
Pages (from-to)	1166-1167
Number of pages	2
Journal	Electronics Letters
Volume	39
Issue number	16
DOIs	https://doi.org/10.1049/el:20030783
State	Published - 7 Aug 2003

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abstract = "Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.",

author = "Kim, {D. J.} and Ko, {J. H.} and Cho, {C. H.} and Park, {Y. I.} and Kang, {D. W.} and Min, {K. S.} and Kim, {D. M.} and Lee, {S. J.} and Shin, {H. S.}",

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AU - Kim, D. J.

AU - Ko, J. H.

AU - Cho, C. H.

AU - Park, Y. I.

AU - Kang, D. W.

AU - Min, K. S.

AU - Kim, D. M.

AU - Lee, S. J.

AU - Shin, H. S.

PY - 2003/8/7

Y1 - 2003/8/7

N2 - Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.

AB - Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.

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JO - Electronics Letters

JF - Electronics Letters

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ER -

High cell-efficiency synchronous MRAM adopting unified bit-line cache

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