High cell-efficiency synchronous MRAM adopting unified bit-line cache

D. J. Kim, J. H. Ko, C. H. Cho, Y. I. Park, D. W. Kang, K. S. Min, D. M. Kim, S. J. Lee, H. S. Shin

Research output: Contribution to journalArticlepeer-review


Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.

Original languageEnglish
Pages (from-to)1166-1167
Number of pages2
JournalElectronics Letters
Issue number16
StatePublished - 7 Aug 2003


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