Gradual bipolar resistive switching in Ni/Si3N4/n+-Si resistive-switching memory device for high-density integration and low-power applications

Sungjun Kim; Sunghun Jung; Min Hwi Kim; Seongjae Cho; Byung Gook Park

doi:10.1016/j.sse.2015.08.003

Gradual bipolar resistive switching in Ni/Si₃N₄/n⁺-Si resistive-switching memory device for high-density integration and low-power applications

Sungjun Kim, Sunghun Jung, Min Hwi Kim, Seongjae Cho, Byung Gook Park

Electronic and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

30 Scopus citations

Abstract

In this work, we report a gradual bipolar resistive switching memory device using Ni/Si₃N₄/n⁺-Si structure. Different reset transitions are observed depending on compliance current (I_COMP). The reset switching becomes abrupt around I_COMP = 10 mA, while gradual reset switching with fine controllability is preserved for the devices with I_COMP < 1 mA. We demonstrate multi-level cell (MLC) operation through the modulation of conducting path by controlling I_COMP and reset stop voltage (V_STOP) for I_COMP < 1 mA. For the devices with I_COMP = 10 mA, low resistance state (LRS) shows Ohmic behavior with metallic conducting paths, while high resistance state (HRS) shows non-Ohmic behavior. Also, it is revealed that LRS and HRS conductions follow space-charge-limited current (SCLC) mechanism in low I_COMP regime (I_COMP < 1 mA).

Original language	English
Pages (from-to)	94-97
Number of pages	4
Journal	Solid-State Electronics
Volume	114
DOIs	https://doi.org/10.1016/j.sse.2015.08.003
State	Published - 2 Dec 2015

Bibliographical note

Publisher Copyright:
© 2015 Elsevier Ltd. All rights reserved.

Keywords

Abrupt reset
Gradual reset
Multi-level cell (MLC)
Resistive switching
SiN-based RRAM
Space-charge-limited current (SCLC)

Access to Document

10.1016/j.sse.2015.08.003

Cite this

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title = "Gradual bipolar resistive switching in Ni/Si3N4/n+-Si resistive-switching memory device for high-density integration and low-power applications",

abstract = "In this work, we report a gradual bipolar resistive switching memory device using Ni/Si3N4/n+-Si structure. Different reset transitions are observed depending on compliance current (ICOMP). The reset switching becomes abrupt around ICOMP = 10 mA, while gradual reset switching with fine controllability is preserved for the devices with ICOMP < 1 mA. We demonstrate multi-level cell (MLC) operation through the modulation of conducting path by controlling ICOMP and reset stop voltage (VSTOP) for ICOMP < 1 mA. For the devices with ICOMP = 10 mA, low resistance state (LRS) shows Ohmic behavior with metallic conducting paths, while high resistance state (HRS) shows non-Ohmic behavior. Also, it is revealed that LRS and HRS conductions follow space-charge-limited current (SCLC) mechanism in low ICOMP regime (ICOMP < 1 mA).",

keywords = "Abrupt reset, Gradual reset, Multi-level cell (MLC), Resistive switching, SiN-based RRAM, Space-charge-limited current (SCLC)",

author = "Sungjun Kim and Sunghun Jung and Kim, {Min Hwi} and Seongjae Cho and Park, {Byung Gook}",

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AU - Kim, Sungjun

AU - Jung, Sunghun

AU - Kim, Min Hwi

AU - Cho, Seongjae

AU - Park, Byung Gook

PY - 2015/12/2

Y1 - 2015/12/2

N2 - In this work, we report a gradual bipolar resistive switching memory device using Ni/Si3N4/n+-Si structure. Different reset transitions are observed depending on compliance current (ICOMP). The reset switching becomes abrupt around ICOMP = 10 mA, while gradual reset switching with fine controllability is preserved for the devices with ICOMP < 1 mA. We demonstrate multi-level cell (MLC) operation through the modulation of conducting path by controlling ICOMP and reset stop voltage (VSTOP) for ICOMP < 1 mA. For the devices with ICOMP = 10 mA, low resistance state (LRS) shows Ohmic behavior with metallic conducting paths, while high resistance state (HRS) shows non-Ohmic behavior. Also, it is revealed that LRS and HRS conductions follow space-charge-limited current (SCLC) mechanism in low ICOMP regime (ICOMP < 1 mA).

AB - In this work, we report a gradual bipolar resistive switching memory device using Ni/Si3N4/n+-Si structure. Different reset transitions are observed depending on compliance current (ICOMP). The reset switching becomes abrupt around ICOMP = 10 mA, while gradual reset switching with fine controllability is preserved for the devices with ICOMP < 1 mA. We demonstrate multi-level cell (MLC) operation through the modulation of conducting path by controlling ICOMP and reset stop voltage (VSTOP) for ICOMP < 1 mA. For the devices with ICOMP = 10 mA, low resistance state (LRS) shows Ohmic behavior with metallic conducting paths, while high resistance state (HRS) shows non-Ohmic behavior. Also, it is revealed that LRS and HRS conductions follow space-charge-limited current (SCLC) mechanism in low ICOMP regime (ICOMP < 1 mA).

KW - Abrupt reset

KW - Gradual reset

KW - Multi-level cell (MLC)

KW - Resistive switching

KW - SiN-based RRAM

KW - Space-charge-limited current (SCLC)

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