Gated Twin-Bit (GTB) nonvolatile memory device and its operation

  • Seongjae Cho
  • , Il Han Park
  • , Jung Hoon Lee
  • , Jang Gn Yun
  • , Doo Hyun Kim
  • , Gil Sung Lee
  • , Hyungcheol Shin
  • , Jong Duk Lee
  • , Byung Gook Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this study, a nonvolatile memory (NVM) device with a novel 3-dimensional structure is introduced. The device is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between pillars can be removed and additional gates called cut-off gates help the operation. In this sense, GTB NVM device is considered as the ultimate form of 3-D nonvolatile memory device based on double-gate structure. Also, the operation is validated by simulation works.

Original languageEnglish
Title of host publicationIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs
StatePublished - 2008
EventIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States
Duration: 15 Jun 200816 Jun 2008

Publication series

NameIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Conference

ConferenceIEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
Country/TerritoryUnited States
CityHonolulu, HI
Period15/06/0816/06/08

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